pred.isa (6272:fa79e8f9ab41) pred.isa (6273:e46f6767b2c0)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 87 unchanged lines hidden (view full) ---

96 DPRINTF(Arm, "in = %%d\\n", _in);
97 DPRINTF(Arm, "iz = %%d\\n", _iz);
98 DPRINTF(Arm, "ic = %%d\\n", _ic);
99 DPRINTF(Arm, "iv = %%d\\n", _iv);
100 '''
101
102}};
103
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 87 unchanged lines hidden (view full) ---

96 DPRINTF(Arm, "in = %%d\\n", _in);
97 DPRINTF(Arm, "iz = %%d\\n", _iz);
98 DPRINTF(Arm, "ic = %%d\\n", _ic);
99 DPRINTF(Arm, "iv = %%d\\n", _iv);
100 '''
101
102}};
103
104def format DataOp(code, icValue, ivValue) {{
104def format DataOp(code, icValue = {{ }},
105 ivValue = {{ Cpsr<28:> }}) {{
105 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs,
106 shift, Cpsr<29:0>);
107 op2 = op2;''' + code
108 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
109 shift, Cpsr<29:0>);
110 op2 = op2;''' + code
106 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs,
107 shift, Cpsr<29:0>);
108 op2 = op2;''' + code
109 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
110 shift, Cpsr<29:0>);
111 op2 = op2;''' + code
112 if icValue == " ":
113 icValueReg = 'shift_carry_rs(Rm, Rs, shift, Cpsr<29:>)'
114 icValueImm = 'shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)'
115 else:
116 icValueReg = icValue
117 icValueImm = icValue
118 regCcCode = calcCcCode % {"icValue" : icValueReg,
119 "ivValue" : ivValue}
120 immCcCode = calcCcCode % {"icValue" : icValueImm,
121 "ivValue" : ivValue}
111 regIop = InstObjParams(name, Name, 'PredIntOp',
112 {"code": regCode,
113 "predicate_test": predicateTest})
114 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
115 {"code": immCode,
116 "predicate_test": predicateTest})
117 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
122 regIop = InstObjParams(name, Name, 'PredIntOp',
123 {"code": regCode,
124 "predicate_test": predicateTest})
125 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
126 {"code": immCode,
127 "predicate_test": predicateTest})
128 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
118 {"code": regCode + calcCcCode % vars(),
129 {"code": regCode + regCcCode,
119 "predicate_test": predicateTest})
120 immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
130 "predicate_test": predicateTest})
131 immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
121 {"code": immCode + calcCcCode % vars(),
132 {"code": immCode + immCcCode,
122 "predicate_test": predicateTest})
123 header_output = BasicDeclare.subst(regIop) + \
124 BasicDeclare.subst(immIop) + \
125 BasicDeclare.subst(regCcIop) + \
126 BasicDeclare.subst(immCcIop)
127 decoder_output = BasicConstructor.subst(regIop) + \
128 BasicConstructor.subst(immIop) + \
129 BasicConstructor.subst(regCcIop) + \
130 BasicConstructor.subst(immCcIop)
131 exec_output = PredOpExecute.subst(regIop) + \
132 PredOpExecute.subst(immIop) + \
133 PredOpExecute.subst(regCcIop) + \
134 PredOpExecute.subst(immCcIop)
135 decode_block = DataDecode.subst(regIop)
136}};
137
133 "predicate_test": predicateTest})
134 header_output = BasicDeclare.subst(regIop) + \
135 BasicDeclare.subst(immIop) + \
136 BasicDeclare.subst(regCcIop) + \
137 BasicDeclare.subst(immCcIop)
138 decoder_output = BasicConstructor.subst(regIop) + \
139 BasicConstructor.subst(immIop) + \
140 BasicConstructor.subst(regCcIop) + \
141 BasicConstructor.subst(immCcIop)
142 exec_output = PredOpExecute.subst(regIop) + \
143 PredOpExecute.subst(immIop) + \
144 PredOpExecute.subst(regCcIop) + \
145 PredOpExecute.subst(immCcIop)
146 decode_block = DataDecode.subst(regIop)
147}};
148
138def format DataImmOp(code, icValue, ivValue) {{
149def format DataImmOp(code,
150 icValue = {{ (rotate ? rotated_carry:Cpsr<29:>) }},
151 ivValue = {{ Cpsr<28:> }}) {{
139 code += "resTemp = resTemp;"
140 iop = InstObjParams(name, Name, 'PredImmOp',
141 {"code": code,
142 "predicate_test": predicateTest})
143 ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
144 {"code": code + calcCcCode % vars(),
145 "predicate_test": predicateTest})
146 header_output = BasicDeclare.subst(iop) + \

--- 71 unchanged lines hidden --- 		152 code += "resTemp = resTemp;"
153 iop = InstObjParams(name, Name, 'PredImmOp',
154 {"code": code,
155 "predicate_test": predicateTest})
156 ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
157 {"code": code + calcCcCode % vars(),
158 "predicate_test": predicateTest})
159 header_output = BasicDeclare.subst(iop) + \

--- 71 unchanged lines hidden ---