1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright
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31//////////////////////////////////////////////////////////////////// 32// 33// Predicated Instruction Execution 34// 35 36output header {{ 37#include <iostream> 38
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39 enum ArmPredicateBits {
40 COND_EQ = 0,
41 COND_NE, // 1
42 COND_CS, // 2
43 COND_CC, // 3
44 COND_MI, // 4
45 COND_PL, // 5
46 COND_VS, // 6
47 COND_VC, // 7
48 COND_HI, // 8
49 COND_LS, // 9
50 COND_GE, // 10
51 COND_LT, // 11
52 COND_GT, // 12
53 COND_LE, // 13
54 COND_AL, // 14
55 COND_NV // 15
56 };
57
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39 inline uint32_t 40 rotate_imm(uint32_t immValue, uint32_t rotateValue) 41 { 42 return ((immValue >> (int)(rotateValue & 31)) | 43 (immValue << (32 - (int)(rotateValue & 31)))); 44 } 45
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65 inline uint32_t nSet(uint32_t cpsr) { return cpsr & (1<<31); }
66 inline uint32_t zSet(uint32_t cpsr) { return cpsr & (1<<30); }
67 inline uint32_t cSet(uint32_t cpsr) { return cpsr & (1<<29); }
68 inline uint32_t vSet(uint32_t cpsr) { return cpsr & (1<<28); }
69
70 inline bool arm_predicate(uint32_t cpsr, uint32_t predBits)
71 {
72
73 enum ArmPredicateBits armPredBits = (enum ArmPredicateBits) predBits;
74 uint32_t result = 0;
75 switch (armPredBits)
76 {
77 case COND_EQ:
78 result = zSet(cpsr); break;
79 case COND_NE:
80 result = !zSet(cpsr); break;
81 case COND_CS:
82 result = cSet(cpsr); break;
83 case COND_CC:
84 result = !cSet(cpsr); break;
85 case COND_MI:
86 result = nSet(cpsr); break;
87 case COND_PL:
88 result = !nSet(cpsr); break;
89 case COND_VS:
90 result = vSet(cpsr); break;
91 case COND_VC:
92 result = !vSet(cpsr); break;
93 case COND_HI:
94 result = cSet(cpsr) && !zSet(cpsr); break;
95 case COND_LS:
96 result = !cSet(cpsr) || zSet(cpsr); break;
97 case COND_GE:
98 result = (!nSet(cpsr) && !vSet(cpsr)) || (nSet(cpsr) && vSet(cpsr)); break;
99 case COND_LT:
100 result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) && vSet(cpsr)); break;
101 case COND_GT:
102 result = (!nSet(cpsr) && !vSet(cpsr) && !zSet(cpsr)) || (nSet(cpsr) && vSet(cpsr) && !zSet(cpsr)); break;
103 case COND_LE:
104 result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) && vSet(cpsr)) || zSet(cpsr); break;
105 case COND_AL: result = 1; break;
106 case COND_NV: result = 0; break;
107 default:
108 fprintf(stderr, "Unhandled predicate condition: %d\n", armPredBits);
109 exit(1);
110 }
111 if (result)
112 return true;
113 else
114 return false;
115 }
116
117
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46 /** 47 * Base class for predicated integer operations. 48 */ 49 class PredOp : public ArmStaticInst 50 {
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123 protected:
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51 protected: |
52
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125 uint32_t condCode;
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53 ArmISA::ConditionCode condCode; |
54
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127 /// Constructor
128 PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
129 ArmStaticInst(mnem, _machInst, __opClass),
130 condCode(COND_CODE)
131 {
132 }
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55 /// Constructor 56 PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 57 ArmStaticInst(mnem, _machInst, __opClass), 58 condCode((ArmISA::ConditionCode)COND_CODE) 59 { 60 } |
61
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134 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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62 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; |
63 }; 64 65 /** 66 * Base class for predicated immediate operations. 67 */ 68 class PredImmOp : public PredOp 69 { 70 protected:
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166 { 167 Fault fault = NoFault; 168 169 %(fp_enable_check)s; 170 %(op_decl)s; 171 %(op_rd)s; 172 %(code)s; 173
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246 if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
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174 if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) |
175 { 176 if (fault == NoFault) 177 { 178 %(op_wb)s; 179 } 180 } 181 else 182 return NoFault;
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