pred.isa (8304:16911ff780d3) pred.isa (11320:42ecb523c64a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43let {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43let {{
44
44
45 calcCcCode = '''
46 if (%(canOverflow)s){
47 cprintf("canOverflow: %%d\\n", Rd < resTemp);
48 CpsrQ = (Rd < resTemp) ? 1 << 27 : 0;
49 } else {
50 uint16_t _ic, _iv, _iz, _in;
51 _in = (resTemp >> %(negBit)d);
52 _iz = (resTemp == 0);
53 _iv = %(ivValue)s;
54 _ic = %(icValue)s;
45 calcCcCode = '''
46 if (%(canOverflow)s){
47 cprintf("canOverflow: %%d\\n", Rd < resTemp);
48 CpsrQ = (Rd < resTemp) ? 1 << 27 : 0;
49 } else {
50 uint16_t _ic, _iv, _iz, _in;
51 _in = (resTemp >> %(negBit)d);
52 _iz = (resTemp == 0);
53 _iv = %(ivValue)s;
54 _ic = %(icValue)s;
55
55
56 CondCodesNZ = (_in << 1) | (_iz);
57 CondCodesC = _ic;
58 CondCodesV = _iv;
59
60 DPRINTF(Arm, "in = %%d\\n", _in);
61 DPRINTF(Arm, "iz = %%d\\n", _iz);
62 DPRINTF(Arm, "ic = %%d\\n", _ic);
63 DPRINTF(Arm, "iv = %%d\\n", _iv);
64 }
65 '''
66}};
67
68let {{
69 def getCcCode(flagtype):
70 icReg = icImm = iv = ''
71 negBit = 31
72 canOverflow = 'false'
73
74 if flagtype == "none":
75 icReg = icImm = 'CondCodesC'
76 iv = 'CondCodesV'
77 elif flagtype == "llbit":
78 icReg = icImm = 'CondCodesC'
79 iv = 'CondCodesV'
80 negBit = 63
81 elif flagtype == "overflow":
56 CondCodesNZ = (_in << 1) | (_iz);
57 CondCodesC = _ic;
58 CondCodesV = _iv;
59
60 DPRINTF(Arm, "in = %%d\\n", _in);
61 DPRINTF(Arm, "iz = %%d\\n", _iz);
62 DPRINTF(Arm, "ic = %%d\\n", _ic);
63 DPRINTF(Arm, "iv = %%d\\n", _iv);
64 }
65 '''
66}};
67
68let {{
69 def getCcCode(flagtype):
70 icReg = icImm = iv = ''
71 negBit = 31
72 canOverflow = 'false'
73
74 if flagtype == "none":
75 icReg = icImm = 'CondCodesC'
76 iv = 'CondCodesV'
77 elif flagtype == "llbit":
78 icReg = icImm = 'CondCodesC'
79 iv = 'CondCodesV'
80 negBit = 63
81 elif flagtype == "overflow":
82 canOverflow = "true"
82 canOverflow = "true"
83 icReg = icImm = iv = '0'
84 elif flagtype == "add":
85 icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
86 iv = 'findOverflow(32, resTemp, Rn, op2)'
87 elif flagtype == "sub":
88 icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)'
89 iv = 'findOverflow(32, resTemp, Rn, ~op2)'
90 elif flagtype == "rsb":
91 icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
92 iv = 'findOverflow(32, resTemp, op2, ~Rn)'
93 else:
94 icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)'
95 icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)'
96 iv = 'CondCodesV'
83 icReg = icImm = iv = '0'
84 elif flagtype == "add":
85 icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
86 iv = 'findOverflow(32, resTemp, Rn, op2)'
87 elif flagtype == "sub":
88 icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)'
89 iv = 'findOverflow(32, resTemp, Rn, ~op2)'
90 elif flagtype == "rsb":
91 icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
92 iv = 'findOverflow(32, resTemp, op2, ~Rn)'
93 else:
94 icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)'
95 icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)'
96 iv = 'CondCodesV'
97 return (calcCcCode % {"icValue" : icReg,
98 "ivValue" : iv,
97 return (calcCcCode % {"icValue" : icReg,
98 "ivValue" : iv,
99 "negBit" : negBit,
100 "canOverflow" : canOverflow },
99 "negBit" : negBit,
100 "canOverflow" : canOverflow },
101 calcCcCode % {"icValue" : icImm,
102 "ivValue" : iv,
101 calcCcCode % {"icValue" : icImm,
102 "ivValue" : iv,
103 "negBit" : negBit,
104 "canOverflow" : canOverflow })
105
106 def getImmCcCode(flagtype):
107 ivValue = icValue = ''
108 negBit = 31
109 canOverflow = 'false'
110 if flagtype == "none":
111 icValue = 'CondCodesC'
112 ivValue = 'CondCodesV'
113 elif flagtype == "llbit":
114 icValue = 'CondCodesC'
115 ivValue = 'CondCodesV'
116 negBit = 63
117 elif flagtype == "overflow":
118 icVaule = ivValue = '0'
103 "negBit" : negBit,
104 "canOverflow" : canOverflow })
105
106 def getImmCcCode(flagtype):
107 ivValue = icValue = ''
108 negBit = 31
109 canOverflow = 'false'
110 if flagtype == "none":
111 icValue = 'CondCodesC'
112 ivValue = 'CondCodesV'
113 elif flagtype == "llbit":
114 icValue = 'CondCodesC'
115 ivValue = 'CondCodesV'
116 negBit = 63
117 elif flagtype == "overflow":
118 icVaule = ivValue = '0'
119 canOverflow = "true"
119 canOverflow = "true"
120 elif flagtype == "add":
121 icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
122 ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
123 elif flagtype == "sub":
124 icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)'
125 ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)'
126 elif flagtype == "rsb":
127 icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)'
128 ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
129 elif flagtype == "modImm":
130 icValue = 'rotated_carry'
131 ivValue = 'CondCodesV'
132 else:
133 icValue = '(rotate ? rotated_carry:CondCodesC)'
134 ivValue = 'CondCodesV'
135 return calcCcCode % vars()
136}};
137
138def format DataOp(code, flagtype = logic) {{
139 (regCcCode, immCcCode) = getCcCode(flagtype)
140 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
141 shift, 0);
142 op2 = op2;''' + code
143 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
144 shift, OptShiftRmCondCodesC);
145 op2 = op2;''' + code
146 regIop = InstObjParams(name, Name, 'PredIntOp',
147 {"code": regCode,
148 "predicate_test": pickPredicate(regCode)})
149 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
150 {"code": immCode,
151 "predicate_test": pickPredicate(imm)})
152 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
153 {"code": regCode + regCcCode,
154 "predicate_test": pickPredicate(regCode + regCcCode)})
155 immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
156 {"code": immCode + immCcCode,
157 "predicate_test": pickPredicate(immCode + immCcCode)})
158 header_output = BasicDeclare.subst(regIop) + \
159 BasicDeclare.subst(immIop) + \
160 BasicDeclare.subst(regCcIop) + \
161 BasicDeclare.subst(immCcIop)
162 decoder_output = BasicConstructor.subst(regIop) + \
163 BasicConstructor.subst(immIop) + \
164 BasicConstructor.subst(regCcIop) + \
165 BasicConstructor.subst(immCcIop)
166 exec_output = PredOpExecute.subst(regIop) + \
167 PredOpExecute.subst(immIop) + \
168 PredOpExecute.subst(regCcIop) + \
169 PredOpExecute.subst(immCcIop)
170 decode_block = DataDecode.subst(regIop)
171}};
172
173def format DataImmOp(code, flagtype = logic) {{
174 code += "resTemp = resTemp;"
175 iop = InstObjParams(name, Name, 'PredImmOp',
176 {"code": code,
177 "predicate_test": pickPredicate(code)})
178 ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
179 {"code": code + getImmCcCode(flagtype),
180 "predicate_test": pickPredicate(code + getImmCcCode(flagtype))})
181 header_output = BasicDeclare.subst(iop) + \
182 BasicDeclare.subst(ccIop)
183 decoder_output = BasicConstructor.subst(iop) + \
184 BasicConstructor.subst(ccIop)
185 exec_output = PredOpExecute.subst(iop) + \
186 PredOpExecute.subst(ccIop)
187 decode_block = DataImmDecode.subst(iop)
188}};
189
190def format PredOp(code, *opt_flags) {{
191 iop = InstObjParams(name, Name, 'PredOp',
192 {"code": code,
193 "predicate_test": pickPredicate(code)},
194 opt_flags)
195 header_output = BasicDeclare.subst(iop)
196 decoder_output = BasicConstructor.subst(iop)
197 decode_block = BasicDecode.subst(iop)
198 exec_output = PredOpExecute.subst(iop)
199}};
200
201def format PredImmOp(code, *opt_flags) {{
202 iop = InstObjParams(name, Name, 'PredImmOp',
203 {"code": code,
204 "predicate_test": pickPredicate(code)},
205 opt_flags)
206 header_output = BasicDeclare.subst(iop)
207 decoder_output = BasicConstructor.subst(iop)
208 decode_block = BasicDecode.subst(iop)
209 exec_output = PredOpExecute.subst(iop)
210}};
211
120 elif flagtype == "add":
121 icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
122 ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
123 elif flagtype == "sub":
124 icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)'
125 ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)'
126 elif flagtype == "rsb":
127 icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)'
128 ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
129 elif flagtype == "modImm":
130 icValue = 'rotated_carry'
131 ivValue = 'CondCodesV'
132 else:
133 icValue = '(rotate ? rotated_carry:CondCodesC)'
134 ivValue = 'CondCodesV'
135 return calcCcCode % vars()
136}};
137
138def format DataOp(code, flagtype = logic) {{
139 (regCcCode, immCcCode) = getCcCode(flagtype)
140 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
141 shift, 0);
142 op2 = op2;''' + code
143 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
144 shift, OptShiftRmCondCodesC);
145 op2 = op2;''' + code
146 regIop = InstObjParams(name, Name, 'PredIntOp',
147 {"code": regCode,
148 "predicate_test": pickPredicate(regCode)})
149 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp',
150 {"code": immCode,
151 "predicate_test": pickPredicate(imm)})
152 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
153 {"code": regCode + regCcCode,
154 "predicate_test": pickPredicate(regCode + regCcCode)})
155 immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
156 {"code": immCode + immCcCode,
157 "predicate_test": pickPredicate(immCode + immCcCode)})
158 header_output = BasicDeclare.subst(regIop) + \
159 BasicDeclare.subst(immIop) + \
160 BasicDeclare.subst(regCcIop) + \
161 BasicDeclare.subst(immCcIop)
162 decoder_output = BasicConstructor.subst(regIop) + \
163 BasicConstructor.subst(immIop) + \
164 BasicConstructor.subst(regCcIop) + \
165 BasicConstructor.subst(immCcIop)
166 exec_output = PredOpExecute.subst(regIop) + \
167 PredOpExecute.subst(immIop) + \
168 PredOpExecute.subst(regCcIop) + \
169 PredOpExecute.subst(immCcIop)
170 decode_block = DataDecode.subst(regIop)
171}};
172
173def format DataImmOp(code, flagtype = logic) {{
174 code += "resTemp = resTemp;"
175 iop = InstObjParams(name, Name, 'PredImmOp',
176 {"code": code,
177 "predicate_test": pickPredicate(code)})
178 ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
179 {"code": code + getImmCcCode(flagtype),
180 "predicate_test": pickPredicate(code + getImmCcCode(flagtype))})
181 header_output = BasicDeclare.subst(iop) + \
182 BasicDeclare.subst(ccIop)
183 decoder_output = BasicConstructor.subst(iop) + \
184 BasicConstructor.subst(ccIop)
185 exec_output = PredOpExecute.subst(iop) + \
186 PredOpExecute.subst(ccIop)
187 decode_block = DataImmDecode.subst(iop)
188}};
189
190def format PredOp(code, *opt_flags) {{
191 iop = InstObjParams(name, Name, 'PredOp',
192 {"code": code,
193 "predicate_test": pickPredicate(code)},
194 opt_flags)
195 header_output = BasicDeclare.subst(iop)
196 decoder_output = BasicConstructor.subst(iop)
197 decode_block = BasicDecode.subst(iop)
198 exec_output = PredOpExecute.subst(iop)
199}};
200
201def format PredImmOp(code, *opt_flags) {{
202 iop = InstObjParams(name, Name, 'PredImmOp',
203 {"code": code,
204 "predicate_test": pickPredicate(code)},
205 opt_flags)
206 header_output = BasicDeclare.subst(iop)
207 decoder_output = BasicConstructor.subst(iop)
208 decode_block = BasicDecode.subst(iop)
209 exec_output = PredOpExecute.subst(iop)
210}};
211