data.isa (7316:bb190cb8ee69) data.isa (7408:ee6949c5bb5b)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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847 const uint32_t imm3 = bits(machInst, 8, 6);
848 const uint32_t imm8 = bits(machInst, 7, 0);
849 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
850 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
851 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
852 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
853 switch (bits(machInst, 13, 11)) {
854 case 0x0: // lsl
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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847 const uint32_t imm3 = bits(machInst, 8, 6);
848 const uint32_t imm8 = bits(machInst, 7, 0);
849 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
850 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
851 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
852 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
853 switch (bits(machInst, 13, 11)) {
854 case 0x0: // lsl
855 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
855 if (machInst.itstateMask) {
856 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
857 } else {
858 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
859 }
856 case 0x1: // lsr
860 case 0x1: // lsr
857 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
861 if (machInst.itstateMask) {
862 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
863 } else {
864 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
865 }
858 case 0x2: // asr
866 case 0x2: // asr
859 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
867 if (machInst.itstateMask) {
868 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
869 } else {
870 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
871 }
860 case 0x3:
861 switch (bits(machInst, 10, 9)) {
862 case 0x0:
872 case 0x3:
873 switch (bits(machInst, 10, 9)) {
874 case 0x0:
863 return new AddRegCc(machInst, rd, rn, rm, 0, LSL);
875 if (machInst.itstateMask) {
876 return new AddReg(machInst, rd, rn, rm, 0, LSL);
877 } else {
878 return new AddRegCc(machInst, rd, rn, rm, 0, LSL);
879 }
864 case 0x1:
880 case 0x1:
865 return new SubRegCc(machInst, rd, rn, rm, 0, LSL);
881 if (machInst.itstateMask) {
882 return new SubReg(machInst, rd, rn, rm, 0, LSL);
883 } else {
884 return new SubRegCc(machInst, rd, rn, rm, 0, LSL);
885 }
866 case 0x2:
886 case 0x2:
867 return new AddImmCc(machInst, rd, rn, imm3, true);
887 if (machInst.itstateMask) {
888 return new AddImm(machInst, rd, rn, imm3, true);
889 } else {
890 return new AddImmCc(machInst, rd, rn, imm3, true);
891 }
868 case 0x3:
892 case 0x3:
869 return new SubImmCc(machInst, rd, rn, imm3, true);
893 if (machInst.itstateMask) {
894 return new SubImm(machInst, rd, rn, imm3, true);
895 } else {
896 return new SubImmCc(machInst, rd, rn, imm3, true);
897 }
870 }
871 case 0x4:
898 }
899 case 0x4:
872 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
900 if (machInst.itstateMask) {
901 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false);
902 } else {
903 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
904 }
873 case 0x5:
874 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
875 case 0x6:
905 case 0x5:
906 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
907 case 0x6:
876 return new AddImmCc(machInst, rd8, rd8, imm8, true);
908 if (machInst.itstateMask) {
909 return new AddImm(machInst, rd8, rd8, imm8, true);
910 } else {
911 return new AddImmCc(machInst, rd8, rd8, imm8, true);
912 }
877 case 0x7:
913 case 0x7:
878 return new SubImmCc(machInst, rd8, rd8, imm8, true);
914 if (machInst.itstateMask) {
915 return new SubImm(machInst, rd8, rd8, imm8, true);
916 } else {
917 return new SubImmCc(machInst, rd8, rd8, imm8, true);
918 }
879 }
880 }
881 '''
882}};
883
884def format Thumb16DataProcessing() {{
885 decode_block = '''
886 {
887 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
888 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
889 switch (bits(machInst, 9, 6)) {
890 case 0x0:
919 }
920 }
921 '''
922}};
923
924def format Thumb16DataProcessing() {{
925 decode_block = '''
926 {
927 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
928 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
929 switch (bits(machInst, 9, 6)) {
930 case 0x0:
891 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL);
931 if (machInst.itstateMask) {
932 return new AndReg(machInst, rdn, rdn, rm, 0, LSL);
933 } else {
934 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL);
935 }
892 case 0x1:
936 case 0x1:
893 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL);
937 if (machInst.itstateMask) {
938 return new EorReg(machInst, rdn, rdn, rm, 0, LSL);
939 } else {
940 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL);
941 }
894 case 0x2: //lsl
942 case 0x2: //lsl
895 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
943 if (machInst.itstateMask) {
944 return new MovRegReg(machInst, rdn,
945 INTREG_ZERO, rdn, rm, LSL);
946 } else {
947 return new MovRegRegCc(machInst, rdn,
948 INTREG_ZERO, rdn, rm, LSL);
949 }
896 case 0x3: //lsr
950 case 0x3: //lsr
897 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
951 if (machInst.itstateMask) {
952 return new MovRegReg(machInst, rdn,
953 INTREG_ZERO, rdn, rm, LSR);
954 } else {
955 return new MovRegRegCc(machInst, rdn,
956 INTREG_ZERO, rdn, rm, LSR);
957 }
898 case 0x4: //asr
958 case 0x4: //asr
899 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
959 if (machInst.itstateMask) {
960 return new MovRegReg(machInst, rdn,
961 INTREG_ZERO, rdn, rm, ASR);
962 } else {
963 return new MovRegRegCc(machInst, rdn,
964 INTREG_ZERO, rdn, rm, ASR);
965 }
900 case 0x5:
966 case 0x5:
901 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL);
967 if (machInst.itstateMask) {
968 return new AdcReg(machInst, rdn, rdn, rm, 0, LSL);
969 } else {
970 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL);
971 }
902 case 0x6:
972 case 0x6:
903 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL);
973 if (machInst.itstateMask) {
974 return new SbcReg(machInst, rdn, rdn, rm, 0, LSL);
975 } else {
976 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL);
977 }
904 case 0x7: // ror
978 case 0x7: // ror
905 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
979 if (machInst.itstateMask) {
980 return new MovRegReg(machInst, rdn,
981 INTREG_ZERO, rdn, rm, ROR);
982 } else {
983 return new MovRegRegCc(machInst, rdn,
984 INTREG_ZERO, rdn, rm, ROR);
985 }
906 case 0x8:
907 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
908 case 0x9:
986 case 0x8:
987 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
988 case 0x9:
909 return new RsbImmCc(machInst, rdn, rm, 0, true);
989 if (machInst.itstateMask) {
990 return new RsbImm(machInst, rdn, rm, 0, true);
991 } else {
992 return new RsbImmCc(machInst, rdn, rm, 0, true);
993 }
910 case 0xa:
911 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
912 case 0xb:
913 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
914 case 0xc:
994 case 0xa:
995 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
996 case 0xb:
997 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
998 case 0xc:
915 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL);
999 if (machInst.itstateMask) {
1000 return new OrrReg(machInst, rdn, rdn, rm, 0, LSL);
1001 } else {
1002 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL);
1003 }
916 case 0xd:
1004 case 0xd:
917 return new MulCc(machInst, rdn, rm, rdn);
1005 if (machInst.itstateMask) {
1006 return new Mul(machInst, rdn, rm, rdn);
1007 } else {
1008 return new MulCc(machInst, rdn, rm, rdn);
1009 }
918 case 0xe:
1010 case 0xe:
919 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
1011 if (machInst.itstateMask) {
1012 return new BicReg(machInst, rdn, rdn, rm, 0, LSL);
1013 } else {
1014 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
1015 }
920 case 0xf:
1016 case 0xf:
921 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1017 if (machInst.itstateMask) {
1018 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1019 } else {
1020 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1021 }
922 }
923 }
924 '''
925}};
926
927def format Thumb16SpecDataAndBx() {{
928 decode_block = '''
929 {

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1065 const uint32_t regList = bits(machInst, 7, 0) | (p << 15);
1066 return new LdmStm(machInst, INTREG_SP, true, true, false,
1067 true, true, regList);
1068 }
1069 case 0xe:
1070 return new WarnUnimplemented("bkpt", machInst);
1071 case 0xf:
1072 if (bits(machInst, 3, 0) != 0)
1022 }
1023 }
1024 '''
1025}};
1026
1027def format Thumb16SpecDataAndBx() {{
1028 decode_block = '''
1029 {

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1165 const uint32_t regList = bits(machInst, 7, 0) | (p << 15);
1166 return new LdmStm(machInst, INTREG_SP, true, true, false,
1167 true, true, regList);
1168 }
1169 case 0xe:
1170 return new WarnUnimplemented("bkpt", machInst);
1171 case 0xf:
1172 if (bits(machInst, 3, 0) != 0)
1073 return new WarnUnimplemented("it", machInst);
1173 return new ItInst(machInst);
1074 switch (bits(machInst, 7, 4)) {
1075 case 0x0:
1076 return new NopInst(machInst);
1077 case 0x1:
1078 return new WarnUnimplemented("yield", machInst);
1079 case 0x2:
1080 return new WarnUnimplemented("wfe", machInst);
1081 case 0x3:

--- 313 unchanged lines hidden --- 		1174 switch (bits(machInst, 7, 4)) {
1175 case 0x0:
1176 return new NopInst(machInst);
1177 case 0x1:
1178 return new WarnUnimplemented("yield", machInst);
1179 case 0x2:
1180 return new WarnUnimplemented("wfe", machInst);
1181 case 0x3:

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