data.isa (7258:6e8a3c0a2a40) data.isa (7290:ea9189fbb84f)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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574}};
575
576def format Thumb32DataProcReg() {{
577 decode_block = '''
578 {
579 const uint32_t op1 = bits(machInst, 23, 20);
580 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
581 const uint32_t op2 = bits(machInst, 7, 4);
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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574}};
575
576def format Thumb32DataProcReg() {{
577 decode_block = '''
578 {
579 const uint32_t op1 = bits(machInst, 23, 20);
580 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
581 const uint32_t op2 = bits(machInst, 7, 4);
582 if (bits(machInst, 15, 12) != 0xf) {
583 return new Unknown(machInst);
584 }
582 if (bits(op1, 3) != 1) {
583 if (op2 == 0) {
584 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
585 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
586 switch (bits(op1, 2, 0)) {
587 case 0x0:
588 return new MovRegReg(machInst, rd,
589 INTREG_ZERO, rn, rm, LSL);

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604 INTREG_ZERO, rn, rm, ASR);
605 case 0x6:
606 return new MovRegReg(machInst, rd,
607 INTREG_ZERO, rn, rm, ROR);
608 case 0x7:
609 return new MovRegRegCc(machInst, rd,
610 INTREG_ZERO, rn, rm, ROR);
611 }
585 if (bits(op1, 3) != 1) {
586 if (op2 == 0) {
587 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
588 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
589 switch (bits(op1, 2, 0)) {
590 case 0x0:
591 return new MovRegReg(machInst, rd,
592 INTREG_ZERO, rn, rm, LSL);

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607 INTREG_ZERO, rn, rm, ASR);
608 case 0x6:
609 return new MovRegReg(machInst, rd,
610 INTREG_ZERO, rn, rm, ROR);
611 case 0x7:
612 return new MovRegRegCc(machInst, rd,
613 INTREG_ZERO, rn, rm, ROR);
614 }
612 }
613 {
615 } else if (bits(op2, 3) == 0) {
616 return new Unknown(machInst);
617 } else {
614 const IntRegIndex rd =
615 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
616 const IntRegIndex rm =
617 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
618 const uint32_t rotation =
619 (uint32_t)bits(machInst, 5, 4) << 3;
620 switch (bits(op1, 2, 0)) {
621 case 0x0:

--- 766 unchanged lines hidden --- 		618 const IntRegIndex rd =
619 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
620 const IntRegIndex rm =
621 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
622 const uint32_t rotation =
623 (uint32_t)bits(machInst, 5, 4) << 3;
624 switch (bits(op1, 2, 0)) {
625 case 0x0:

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