data.isa (7252:bba68021edca) data.isa (7255:61445190b527)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUsad() {{
38def format ArmMiscMedia() {{
39 decode_block = '''
40 {
39 decode_block = '''
40 {
41 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
41 const uint32_t op1 = bits(machInst, 22, 20);
42 const uint32_t op2 = bits(machInst, 7, 5);
42 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
43 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
43 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
44 const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
44 const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
45 if (ra == 0xf) {
46 return new Usad8(machInst, rd, rn, rm);
47 } else {
48 return new Usada8(machInst, rd, rn, rm, ra);
45 if (op1 == 0 && op2 == 0) {
46 const IntRegIndex rd =
47 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
48 const IntRegIndex rm =
49 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
50 if (ra == 0xf) {
51 return new Usad8(machInst, rd, rn, rm);
52 } else {
53 return new Usada8(machInst, rd, rn, rm, ra);
54 }
55 } else if (bits(op2, 1, 0) == 0x2) {
56 if (bits(op1, 2, 1) == 0x3) {
57 return new WarnUnimplemented("ubfx", machInst);
58 } else if (bits(op1, 2, 1) == 0x1) {
59 return new WarnUnimplemented("sbfx", machInst);
60 }
61 } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) {
62 if (rn == 0xf) {
63 return new WarnUnimplemented("bfc", machInst);
64 } else {
65 return new WarnUnimplemented("bfi", machInst);
66 }
49 }
67 }
68 return new Unknown(machInst);
50 }
51 '''
52}};
53
54def format ArmDataProcReg() {{
55 pclr = '''
56 return new %(className)ssRegPclr(machInst, %(dest)s,
57 %(op1)s, rm, imm5,

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70 '''
71}};
72
73def format ArmDataProcReg() {{
74 pclr = '''
75 return new %(className)ssRegPclr(machInst, %(dest)s,
76 %(op1)s, rm, imm5,

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