data.isa (7248:f5563135de40) data.isa (7250:40b0a5327df8)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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278 if (a == 0xf) {
279 return new Uxtb(machInst, rd, rotation, rm);
280 } else {
281 return new Uxtab(machInst, rd, rn, rm, rotation);
282 }
283 }
284 break;
285 case 0x7:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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278 if (a == 0xf) {
279 return new Uxtb(machInst, rd, rotation, rm);
280 } else {
281 return new Uxtab(machInst, rd, rn, rm, rotation);
282 }
283 }
284 break;
285 case 0x7:
286 if (op2 == 0x1) {
287 return new WarnUnimplemented("rbit", machInst);
288 } else if (op2 == 0x3) {
286 {
289 const IntRegIndex rn =
290 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
291 const IntRegIndex rd =
292 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
293 const IntRegIndex rm =
294 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
287 const IntRegIndex rn =
288 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
289 const IntRegIndex rd =
290 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
291 const IntRegIndex rm =
292 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
295 const uint32_t rotation =
296 (uint32_t)bits(machInst, 11, 10) << 3;
297 if (a == 0xf) {
298 return new Uxth(machInst, rd, rotation, rm);
299 } else {
300 return new Uxtah(machInst, rd, rn, rm, rotation);
293 if (op2 == 0x1) {
294 return new Rbit(machInst, rd, rm);
295 } else if (op2 == 0x3) {
296 const uint32_t rotation =
297 (uint32_t)bits(machInst, 11, 10) << 3;
298 if (a == 0xf) {
299 return new Uxth(machInst, rd, rotation, rm);
300 } else {
301 return new Uxtah(machInst, rd, rn, rm, rotation);
302 }
303 } else if (op2 == 0x5) {
304 return new Revsh(machInst, rd, rm);
301 }
305 }
302 } else if (op2 == 0x5) {
303 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
304 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
305 return new Revsh(machInst, rd, rm);
306 }
307 break;
308 }
309 return new Unknown(machInst);
310 }
311 '''
312}};
313

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786 break;
787 case 0x1:
788 switch (op2) {
789 case 0x0:
790 return new Rev(machInst, rd, rn);
791 case 0x1:
792 return new Rev16(machInst, rd, rn);
793 case 0x2:
306 }
307 break;
308 }
309 return new Unknown(machInst);
310 }
311 '''
312}};
313

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786 break;
787 case 0x1:
788 switch (op2) {
789 case 0x0:
790 return new Rev(machInst, rd, rn);
791 case 0x1:
792 return new Rev16(machInst, rd, rn);
793 case 0x2:
794 return new WarnUnimplemented("rbit", machInst);
794 return new Rbit(machInst, rd, rm);
795 case 0x3:
796 return new Revsh(machInst, rd, rn);
797 }
798 break;
799 case 0x2:
800 if (op2 == 0) {
801 return new Sel(machInst, rd, rn, rm);
802 }

--- 547 unchanged lines hidden --- 		795 case 0x3:
796 return new Revsh(machInst, rd, rn);
797 }
798 break;
799 case 0x2:
800 if (op2 == 0) {
801 return new Sel(machInst, rd, rn, rm);
802 }

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