data.isa (7237:4c1445a9e72b) data.isa (7240:40a17fb6a9c5)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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151 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
152 } else if (bits(op1, 2, 1) == 3) {
153 return new Usat(machInst, rd, satImm, rn, imm, type);
154 }
155 return new Unknown(machInst);
156 }
157 switch (op1) {
158 case 0x0:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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151 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
152 } else if (bits(op1, 2, 1) == 3) {
153 return new Usat(machInst, rd, satImm, rn, imm, type);
154 }
155 return new Unknown(machInst);
156 }
157 switch (op1) {
158 case 0x0:
159 if (op2 == 0x3) {
159 {
160 const IntRegIndex rn =
161 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
162 const IntRegIndex rd =
163 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
164 const IntRegIndex rm =
165 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
160 const IntRegIndex rn =
161 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
162 const IntRegIndex rd =
163 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
164 const IntRegIndex rm =
165 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
166 const uint32_t rotation =
167 (uint32_t)bits(machInst, 11, 10) << 3;
168 if (a == 0xf) {
169 return new Sxtb16(machInst, rd, rotation, rm);
170 } else {
171 return new Sxtab16(machInst, rd, rn, rm, rotation);
166 if (op2 == 0x3) {
167 const uint32_t rotation =
168 (uint32_t)bits(machInst, 11, 10) << 3;
169 if (a == 0xf) {
170 return new Sxtb16(machInst, rd, rotation, rm);
171 } else {
172 return new Sxtab16(machInst, rd, rn, rm, rotation);
173 }
174 } else if (op2 == 0x5) {
175 return new Sel(machInst, rd, rn, rm);
172 }
176 }
173 } else if (op2 == 0x5) {
174 return new WarnUnimplemented("sel", machInst);
175 }
176 break;
177 case 0x2:
178 if (op2 == 0x1) {
179 const IntRegIndex rn =
180 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
181 const IntRegIndex rd =
182 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);

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740 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL);
741 }
742 break;
743 }
744 }
745 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) {
746 const uint32_t op1 = bits(machInst, 21, 20);
747 const uint32_t op2 = bits(machInst, 5, 4);
177 }
178 break;
179 case 0x2:
180 if (op2 == 0x1) {
181 const IntRegIndex rn =
182 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
183 const IntRegIndex rd =
184 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);

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742 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL);
743 }
744 break;
745 }
746 }
747 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) {
748 const uint32_t op1 = bits(machInst, 21, 20);
749 const uint32_t op2 = bits(machInst, 5, 4);
750 const IntRegIndex rd =
751 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
752 const IntRegIndex rm =
753 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
748 switch (op1) {
749 case 0x0:
754 switch (op1) {
755 case 0x0:
750 {
751 IntRegIndex rd =
752 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
753 IntRegIndex rm =
754 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
755 switch (op2) {
756 case 0x0:
757 return new QaddRegCc(machInst, rd,
758 rm, rn, 0, LSL);
759 case 0x1:
760 return new QdaddRegCc(machInst, rd,
761 rm, rn, 0, LSL);
762 case 0x2:
763 return new QsubRegCc(machInst, rd,
764 rm, rn, 0, LSL);
765 case 0x3:
766 return new QdsubRegCc(machInst, rd,
767 rm, rn, 0, LSL);
768 }
756 switch (op2) {
757 case 0x0:
758 return new QaddRegCc(machInst, rd,
759 rm, rn, 0, LSL);
760 case 0x1:
761 return new QdaddRegCc(machInst, rd,
762 rm, rn, 0, LSL);
763 case 0x2:
764 return new QsubRegCc(machInst, rd,
765 rm, rn, 0, LSL);
766 case 0x3:
767 return new QdsubRegCc(machInst, rd,
768 rm, rn, 0, LSL);
769 }
770 break;
771 case 0x1:
769 }
770 break;
771 case 0x1:
772 {
773 IntRegIndex rd =
774 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
775 IntRegIndex rm = rn;
776 switch (op2) {
777 case 0x0:
778 return new Rev(machInst, rd, rm);
779 case 0x1:
780 return new Rev16(machInst, rd, rm);
781 case 0x2:
782 return new WarnUnimplemented("rbit", machInst);
783 case 0x3:
784 return new Revsh(machInst, rd, rm);
785 }
772 switch (op2) {
773 case 0x0:
774 return new Rev(machInst, rd, rn);
775 case 0x1:
776 return new Rev16(machInst, rd, rn);
777 case 0x2:
778 return new WarnUnimplemented("rbit", machInst);
779 case 0x3:
780 return new Revsh(machInst, rd, rn);
786 }
787 break;
788 case 0x2:
789 if (op2 == 0) {
781 }
782 break;
783 case 0x2:
784 if (op2 == 0) {
790 return new WarnUnimplemented("sel", machInst);
785 return new Sel(machInst, rd, rn, rm);
791 }
792 break;
793 case 0x3:
794 if (op2 == 0) {
795 return new WarnUnimplemented("clz", machInst);
796 }
797 }
798 }

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787 break;
788 case 0x3:
789 if (op2 == 0) {
790 return new WarnUnimplemented("clz", machInst);
791 }
792 }
793 }

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