data.isa (7235:14dcfcf361ef) data.isa (7237:4c1445a9e72b)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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135 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
136 const IntRegIndex rd =
137 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
138 const uint32_t satImm = bits(machInst, 20, 16);
139 const uint32_t imm = bits(machInst, 11, 7);
140 const ArmShiftType type =
141 (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
142 if (op1 == 0) {
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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135 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
136 const IntRegIndex rd =
137 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
138 const uint32_t satImm = bits(machInst, 20, 16);
139 const uint32_t imm = bits(machInst, 11, 7);
140 const ArmShiftType type =
141 (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
142 if (op1 == 0) {
143 return new WarnUnimplemented("pkh", machInst);
143 if (type) {
144 return new PkhtbReg(machInst, rd, (IntRegIndex)a,
145 rn, imm, type);
146 } else {
147 return new PkhbtReg(machInst, rd, (IntRegIndex)a,
148 rn, imm, type);
149 }
144 } else if (bits(op1, 2, 1) == 1) {
145 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
146 } else if (bits(op1, 2, 1) == 3) {
147 return new Usat(machInst, rd, satImm, rn, imm, type);
148 }
149 return new Unknown(machInst);
150 }
151 switch (op1) {

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1279 }
1280 case 0x4:
1281 if (rd == INTREG_PC) {
1282 %(teq)s
1283 } else {
1284 %(eor)s
1285 }
1286 case 0x6:
150 } else if (bits(op1, 2, 1) == 1) {
151 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
152 } else if (bits(op1, 2, 1) == 3) {
153 return new Usat(machInst, rd, satImm, rn, imm, type);
154 }
155 return new Unknown(machInst);
156 }
157 switch (op1) {

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1285 }
1286 case 0x4:
1287 if (rd == INTREG_PC) {
1288 %(teq)s
1289 } else {
1290 %(eor)s
1291 }
1292 case 0x6:
1287 return new WarnUnimplemented("pkh", machInst);
1293 if (type) {
1294 return new PkhtbReg(machInst, rd, rn, rm, amt, type);
1295 } else {
1296 return new PkhbtReg(machInst, rd, rn, rm, amt, type);
1297 }
1288 case 0x8:
1289 if (rd == INTREG_PC) {
1290 %(cmn)s
1291 } else {
1292 %(add)s
1293 }
1294 case 0xa:
1295 %(adc)s

--- 33 unchanged lines hidden --- 		1298 case 0x8:
1299 if (rd == INTREG_PC) {
1300 %(cmn)s
1301 } else {
1302 %(add)s
1303 }
1304 case 0xa:
1305 %(adc)s

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