data.isa (7231:a9fa4128c5c9) data.isa (7235:14dcfcf361ef)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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146 } else if (bits(op1, 2, 1) == 3) {
147 return new Usat(machInst, rd, satImm, rn, imm, type);
148 }
149 return new Unknown(machInst);
150 }
151 switch (op1) {
152 case 0x0:
153 if (op2 == 0x3) {
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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146 } else if (bits(op1, 2, 1) == 3) {
147 return new Usat(machInst, rd, satImm, rn, imm, type);
148 }
149 return new Unknown(machInst);
150 }
151 switch (op1) {
152 case 0x0:
153 if (op2 == 0x3) {
154 const IntRegIndex rn =
155 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
156 const IntRegIndex rd =
157 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
158 const IntRegIndex rm =
159 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
160 const uint32_t rotation =
161 (uint32_t)bits(machInst, 11, 10) << 3;
154 if (a == 0xf) {
162 if (a == 0xf) {
155 return new WarnUnimplemented("sxtb16", machInst);
163 return new Sxtb16(machInst, rd, rotation, rm);
156 } else {
164 } else {
157 return new WarnUnimplemented("sxtab16", machInst);
165 return new Sxtab16(machInst, rd, rn, rm, rotation);
158 }
159 } else if (op2 == 0x5) {
160 return new WarnUnimplemented("sel", machInst);
161 }
162 break;
163 case 0x2:
164 if (op2 == 0x1) {
165 const IntRegIndex rn =
166 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
167 const IntRegIndex rd =
168 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
169 const uint32_t satImm = bits(machInst, 20, 16);
170 return new Ssat16(machInst, rd, satImm + 1, rn);
171 } else if (op2 == 0x3) {
166 }
167 } else if (op2 == 0x5) {
168 return new WarnUnimplemented("sel", machInst);
169 }
170 break;
171 case 0x2:
172 if (op2 == 0x1) {
173 const IntRegIndex rn =
174 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
175 const IntRegIndex rd =
176 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
177 const uint32_t satImm = bits(machInst, 20, 16);
178 return new Ssat16(machInst, rd, satImm + 1, rn);
179 } else if (op2 == 0x3) {
180 const IntRegIndex rn =
181 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
182 const IntRegIndex rd =
183 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
184 const IntRegIndex rm =
185 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
186 const uint32_t rotation =
187 (uint32_t)bits(machInst, 11, 10) << 3;
172 if (a == 0xf) {
188 if (a == 0xf) {
173 return new WarnUnimplemented("sxtb", machInst);
189 return new Sxtb(machInst, rd, rotation, rm);
174 } else {
190 } else {
175 return new WarnUnimplemented("sxtab", machInst);
191 return new Sxtab(machInst, rd, rn, rm, rotation);
176 }
177 }
178 break;
179 case 0x3:
180 if (op2 == 0x1) {
181 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
182 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
183 return new Rev(machInst, rd, rm);
184 } else if (op2 == 0x3) {
192 }
193 }
194 break;
195 case 0x3:
196 if (op2 == 0x1) {
197 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
198 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
199 return new Rev(machInst, rd, rm);
200 } else if (op2 == 0x3) {
201 const IntRegIndex rn =
202 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
203 const IntRegIndex rd =
204 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
205 const IntRegIndex rm =
206 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
207 const uint32_t rotation =
208 (uint32_t)bits(machInst, 11, 10) << 3;
185 if (a == 0xf) {
209 if (a == 0xf) {
186 return new WarnUnimplemented("sxth", machInst);
210 return new Sxth(machInst, rd, rotation, rm);
187 } else {
211 } else {
188 return new WarnUnimplemented("sxtah", machInst);
212 return new Sxtah(machInst, rd, rn, rm, rotation);
189 }
190 } else if (op2 == 0x5) {
191 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
192 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
193 return new Rev16(machInst, rd, rm);
194 }
195 break;
196 case 0x4:
197 if (op2 == 0x3) {
213 }
214 } else if (op2 == 0x5) {
215 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
216 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
217 return new Rev16(machInst, rd, rm);
218 }
219 break;
220 case 0x4:
221 if (op2 == 0x3) {
222 const IntRegIndex rn =
223 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
224 const IntRegIndex rd =
225 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
226 const IntRegIndex rm =
227 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
228 const uint32_t rotation =
229 (uint32_t)bits(machInst, 11, 10) << 3;
198 if (a == 0xf) {
230 if (a == 0xf) {
199 return new WarnUnimplemented("uxtb16", machInst);
231 return new Uxtb16(machInst, rd, rotation, rm);
200 } else {
232 } else {
201 return new WarnUnimplemented("uxtab16", machInst);
233 return new Uxtab16(machInst, rd, rn, rm, rotation);
202 }
203 }
204 break;
205 case 0x6:
206 if (op2 == 0x1) {
207 const IntRegIndex rn =
208 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
209 const IntRegIndex rd =
210 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
211 const uint32_t satImm = bits(machInst, 20, 16);
212 return new Usat16(machInst, rd, satImm, rn);
213 } else if (op2 == 0x3) {
234 }
235 }
236 break;
237 case 0x6:
238 if (op2 == 0x1) {
239 const IntRegIndex rn =
240 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
241 const IntRegIndex rd =
242 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
243 const uint32_t satImm = bits(machInst, 20, 16);
244 return new Usat16(machInst, rd, satImm, rn);
245 } else if (op2 == 0x3) {
246 const IntRegIndex rn =
247 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
248 const IntRegIndex rd =
249 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
250 const IntRegIndex rm =
251 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
252 const uint32_t rotation =
253 (uint32_t)bits(machInst, 11, 10) << 3;
214 if (a == 0xf) {
254 if (a == 0xf) {
215 return new WarnUnimplemented("uxtb", machInst);
255 return new Uxtb(machInst, rd, rotation, rm);
216 } else {
256 } else {
217 return new WarnUnimplemented("uxtab", machInst);
257 return new Uxtab(machInst, rd, rn, rm, rotation);
218 }
219 }
220 break;
221 case 0x7:
222 if (op2 == 0x1) {
223 return new WarnUnimplemented("rbit", machInst);
224 } else if (op2 == 0x3) {
258 }
259 }
260 break;
261 case 0x7:
262 if (op2 == 0x1) {
263 return new WarnUnimplemented("rbit", machInst);
264 } else if (op2 == 0x3) {
265 const IntRegIndex rn =
266 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
267 const IntRegIndex rd =
268 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
269 const IntRegIndex rm =
270 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
271 const uint32_t rotation =
272 (uint32_t)bits(machInst, 11, 10) << 3;
225 if (a == 0xf) {
273 if (a == 0xf) {
226 return new WarnUnimplemented("uxth", machInst);
274 return new Uxth(machInst, rd, rotation, rm);
227 } else {
275 } else {
228 return new WarnUnimplemented("uxtah", machInst);
276 return new Uxtah(machInst, rd, rn, rm, rotation);
229 }
230 } else if (op2 == 0x5) {
231 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
232 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
233 return new Revsh(machInst, rd, rm);
234 }
235 break;
236 }

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510 case 0x6:
511 return new MovRegReg(machInst, rd,
512 INTREG_ZERO, rn, rm, ROR);
513 case 0x7:
514 return new MovRegRegCc(machInst, rd,
515 INTREG_ZERO, rn, rm, ROR);
516 }
517 }
277 }
278 } else if (op2 == 0x5) {
279 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
280 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
281 return new Revsh(machInst, rd, rm);
282 }
283 break;
284 }

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558 case 0x6:
559 return new MovRegReg(machInst, rd,
560 INTREG_ZERO, rn, rm, ROR);
561 case 0x7:
562 return new MovRegRegCc(machInst, rd,
563 INTREG_ZERO, rn, rm, ROR);
564 }
565 }
518 switch (bits(op1, 2, 0)) {
519 case 0x0:
520 if (rn == 0xf) {
521 return new WarnUnimplemented("sxth", machInst);
522 } else {
523 return new WarnUnimplemented("sxtah", machInst);
566 {
567 const IntRegIndex rd =
568 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
569 const IntRegIndex rm =
570 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
571 const uint32_t rotation =
572 (uint32_t)bits(machInst, 5, 4) << 3;
573 switch (bits(op1, 2, 0)) {
574 case 0x0:
575 if (rn == 0xf) {
576 return new Sxth(machInst, rd, rotation, rm);
577 } else {
578 return new Sxtah(machInst, rd, rn, rm, rotation);
579 }
580 case 0x1:
581 if (rn == 0xf) {
582 return new Uxth(machInst, rd, rotation, rm);
583 } else {
584 return new Uxtah(machInst, rd, rn, rm, rotation);
585 }
586 case 0x2:
587 if (rn == 0xf) {
588 return new Sxtb16(machInst, rd, rotation, rm);
589 } else {
590 return new Sxtab16(machInst, rd, rn, rm, rotation);
591 }
592 case 0x3:
593 if (rn == 0xf) {
594 return new Uxtb16(machInst, rd, rotation, rm);
595 } else {
596 return new Uxtab16(machInst, rd, rn, rm, rotation);
597 }
598 case 0x4:
599 if (rn == 0xf) {
600 return new Sxtb(machInst, rd, rotation, rm);
601 } else {
602 return new Sxtab(machInst, rd, rn, rm, rotation);
603 }
604 case 0x5:
605 if (rn == 0xf) {
606 return new Uxtb(machInst, rd, rotation, rm);
607 } else {
608 return new Uxtab(machInst, rd, rn, rm, rotation);
609 }
610 default:
611 return new Unknown(machInst);
524 }
612 }
525 case 0x1:
526 if (rn == 0xf) {
527 return new WarnUnimplemented("uxth", machInst);
528 } else {
529 return new WarnUnimplemented("uxtah", machInst);
530 }
531 case 0x2:
532 if (rn == 0xf) {
533 return new WarnUnimplemented("sxtb16", machInst);
534 } else {
535 return new WarnUnimplemented("sxtab16", machInst);
536 }
537 case 0x3:
538 if (rn == 0xf) {
539 return new WarnUnimplemented("uxtb16", machInst);
540 } else {
541 return new WarnUnimplemented("uxtab16", machInst);
542 }
543 case 0x4:
544 if (rn == 0xf) {
545 return new WarnUnimplemented("sxtb", machInst);
546 } else {
547 return new WarnUnimplemented("sxtab", machInst);
548 }
549 case 0x5:
550 if (rn == 0xf) {
551 return new WarnUnimplemented("uxtb", machInst);
552 } else {
553 return new WarnUnimplemented("uxtab", machInst);
554 }
555 default:
556 return new Unknown(machInst);
557 }
558 } else {
559 if (bits(op2, 3) == 0) {
560 const IntRegIndex rd =
561 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
562 const IntRegIndex rm =
563 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
564 if (bits(op2, 2) == 0x0) {

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886 bits(machInst, 6, 0) << 2, true);
887 }
888 case 0x1:
889 return new Cbz(machInst,
890 (bits(machInst, 9) << 6) |
891 (bits(machInst, 7, 3) << 1),
892 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
893 case 0x2:
613 }
614 } else {
615 if (bits(op2, 3) == 0) {
616 const IntRegIndex rd =
617 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
618 const IntRegIndex rm =
619 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
620 if (bits(op2, 2) == 0x0) {

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942 bits(machInst, 6, 0) << 2, true);
943 }
944 case 0x1:
945 return new Cbz(machInst,
946 (bits(machInst, 9) << 6) |
947 (bits(machInst, 7, 3) << 1),
948 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
949 case 0x2:
894 switch (bits(machInst, 7, 6)) {
895 case 0x0:
896 return new WarnUnimplemented("sxth", machInst);
897 case 0x1:
898 return new WarnUnimplemented("sxtb", machInst);
899 case 0x2:
900 return new WarnUnimplemented("uxth", machInst);
901 case 0x3:
902 return new WarnUnimplemented("uxtb", machInst);
950 {
951 const IntRegIndex rd =
952 (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
953 const IntRegIndex rm =
954 (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
955 switch (bits(machInst, 7, 6)) {
956 case 0x0:
957 return new Sxth(machInst, rd, 0, rm);
958 case 0x1:
959 return new Sxtb(machInst, rd, 0, rm);
960 case 0x2:
961 return new Uxth(machInst, rd, 0, rm);
962 case 0x3:
963 return new Uxtb(machInst, rd, 0, rm);
964 }
903 }
904 case 0x3:
905 return new Cbz(machInst,
906 (bits(machInst, 9) << 6) |
907 (bits(machInst, 7, 3) << 1),
908 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
909 case 0x4:
910 case 0x5:

--- 356 unchanged lines hidden --- 		965 }
966 case 0x3:
967 return new Cbz(machInst,
968 (bits(machInst, 9) << 6) |
969 (bits(machInst, 7, 3) << 1),
970 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
971 case 0x4:
972 case 0x5:

--- 356 unchanged lines hidden ---