data.isa (7227:6f435f54b1fb) data.isa (7231:a9fa4128c5c9)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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279 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
280 case 0x7:
281 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
282 }
283 break;
284 case 0x3:
285 switch (op2) {
286 case 0x0:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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279 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
280 case 0x7:
281 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
282 }
283 break;
284 case 0x3:
285 switch (op2) {
286 case 0x0:
287 return new WarnUnimplemented("shadd16", machInst);
287 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL);
288 case 0x1:
288 case 0x1:
289 return new WarnUnimplemented("shasx", machInst);
289 return new ShasxReg(machInst, rd, rn, rm, 0, LSL);
290 case 0x2:
290 case 0x2:
291 return new WarnUnimplemented("shsax", machInst);
291 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL);
292 case 0x3:
292 case 0x3:
293 return new WarnUnimplemented("shsub16", machInst);
293 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL);
294 case 0x4:
294 case 0x4:
295 return new WarnUnimplemented("shadd8", machInst);
295 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL);
296 case 0x7:
296 case 0x7:
297 return new WarnUnimplemented("shsub8", machInst);
297 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL);
298 }
299 break;
300 }
301 } else {
302 switch (op1) {
303 case 0x1:
304 switch (op2) {
305 case 0x0:

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330 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
331 case 0x7:
332 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
333 }
334 break;
335 case 0x3:
336 switch (op2) {
337 case 0x0:
298 }
299 break;
300 }
301 } else {
302 switch (op1) {
303 case 0x1:
304 switch (op2) {
305 case 0x0:

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330 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
331 case 0x7:
332 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
333 }
334 break;
335 case 0x3:
336 switch (op2) {
337 case 0x0:
338 return new WarnUnimplemented("uhadd16", machInst);
338 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL);
339 case 0x1:
339 case 0x1:
340 return new WarnUnimplemented("uhasx", machInst);
340 return new UhasxReg(machInst, rd, rn, rm, 0, LSL);
341 case 0x2:
341 case 0x2:
342 return new WarnUnimplemented("uhsax", machInst);
342 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL);
343 case 0x3:
343 case 0x3:
344 return new WarnUnimplemented("uhsub16", machInst);
344 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL);
345 case 0x4:
345 case 0x4:
346 return new WarnUnimplemented("uhadd8", machInst);
346 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL);
347 case 0x7:
347 case 0x7:
348 return new WarnUnimplemented("uhsub8", machInst);
348 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL);
349 }
350 break;
351 }
352 }
353 return new Unknown(machInst);
354 }
355 '''
356}};

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601 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
602 case 0x4:
603 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
604 }
605 break;
606 case 0x2:
607 switch (op1) {
608 case 0x1:
349 }
350 break;
351 }
352 }
353 return new Unknown(machInst);
354 }
355 '''
356}};

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601 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
602 case 0x4:
603 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
604 }
605 break;
606 case 0x2:
607 switch (op1) {
608 case 0x1:
609 return new WarnUnimplemented("shadd16", machInst);
609 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL);
610 case 0x2:
610 case 0x2:
611 return new WarnUnimplemented("shasx", machInst);
611 return new ShasxReg(machInst, rd, rn, rm, 0, LSL);
612 case 0x6:
612 case 0x6:
613 return new WarnUnimplemented("shsax", machInst);
613 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL);
614 case 0x5:
614 case 0x5:
615 return new WarnUnimplemented("shsub16", machInst);
615 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL);
616 case 0x0:
616 case 0x0:
617 return new WarnUnimplemented("shadd8", machInst);
617 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL);
618 case 0x4:
618 case 0x4:
619 return new WarnUnimplemented("shsub8", machInst);
619 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL);
620 }
621 break;
622 }
623 } else {
624 const uint32_t op1 = bits(machInst, 22, 20);
625 const uint32_t op2 = bits(machInst, 5, 4);
626 switch (op2) {
627 case 0x0:

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660 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
661 case 0x4:
662 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
663 }
664 break;
665 case 0x2:
666 switch (op1) {
667 case 0x1:
620 }
621 break;
622 }
623 } else {
624 const uint32_t op1 = bits(machInst, 22, 20);
625 const uint32_t op2 = bits(machInst, 5, 4);
626 switch (op2) {
627 case 0x0:

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660 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
661 case 0x4:
662 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
663 }
664 break;
665 case 0x2:
666 switch (op1) {
667 case 0x1:
668 return new WarnUnimplemented("uhadd16", machInst);
668 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL);
669 case 0x2:
669 case 0x2:
670 return new WarnUnimplemented("uhasx", machInst);
670 return new UhasxReg(machInst, rd, rn, rm, 0, LSL);
671 case 0x6:
671 case 0x6:
672 return new WarnUnimplemented("uhsax", machInst);
672 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL);
673 case 0x5:
673 case 0x5:
674 return new WarnUnimplemented("uhsub16", machInst);
674 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL);
675 case 0x0:
675 case 0x0:
676 return new WarnUnimplemented("uhadd8", machInst);
676 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL);
677 case 0x4:
677 case 0x4:
678 return new WarnUnimplemented("uhsub8", machInst);
678 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL);
679 }
680 break;
681 }
682 }
683 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) {
684 const uint32_t op1 = bits(machInst, 21, 20);
685 const uint32_t op2 = bits(machInst, 5, 4);
686 switch (op1) {

--- 580 unchanged lines hidden --- 		679 }
680 break;
681 }
682 }
683 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) {
684 const uint32_t op1 = bits(machInst, 21, 20);
685 const uint32_t op2 = bits(machInst, 5, 4);
686 switch (op1) {

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