data.isa (7224:7d22b6d6093f) data.isa (7227:6f435f54b1fb)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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126
127def format ArmPackUnpackSatReverse() {{
128 decode_block = '''
129 {
130 const uint32_t op1 = bits(machInst, 22, 20);
131 const uint32_t a = bits(machInst, 19, 16);
132 const uint32_t op2 = bits(machInst, 7, 5);
133 if (bits(op2, 0) == 0) {
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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126
127def format ArmPackUnpackSatReverse() {{
128 decode_block = '''
129 {
130 const uint32_t op1 = bits(machInst, 22, 20);
131 const uint32_t a = bits(machInst, 19, 16);
132 const uint32_t op2 = bits(machInst, 7, 5);
133 if (bits(op2, 0) == 0) {
134 const IntRegIndex rn =
135 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
136 const IntRegIndex rd =
137 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
138 const uint32_t satImm = bits(machInst, 20, 16);
139 const uint32_t imm = bits(machInst, 11, 7);
140 const ArmShiftType type =
141 (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
134 if (op1 == 0) {
135 return new WarnUnimplemented("pkh", machInst);
136 } else if (bits(op1, 2, 1) == 1) {
142 if (op1 == 0) {
143 return new WarnUnimplemented("pkh", machInst);
144 } else if (bits(op1, 2, 1) == 1) {
137 return new WarnUnimplemented("ssat", machInst);
145 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
138 } else if (bits(op1, 2, 1) == 3) {
146 } else if (bits(op1, 2, 1) == 3) {
139 return new WarnUnimplemented("usat", machInst);
147 return new Usat(machInst, rd, satImm, rn, imm, type);
140 }
141 return new Unknown(machInst);
142 }
143 switch (op1) {
144 case 0x0:
145 if (op2 == 0x3) {
146 if (a == 0xf) {
147 return new WarnUnimplemented("sxtb16", machInst);
148 } else {
149 return new WarnUnimplemented("sxtab16", machInst);
150 }
151 } else if (op2 == 0x5) {
152 return new WarnUnimplemented("sel", machInst);
153 }
154 break;
155 case 0x2:
156 if (op2 == 0x1) {
148 }
149 return new Unknown(machInst);
150 }
151 switch (op1) {
152 case 0x0:
153 if (op2 == 0x3) {
154 if (a == 0xf) {
155 return new WarnUnimplemented("sxtb16", machInst);
156 } else {
157 return new WarnUnimplemented("sxtab16", machInst);
158 }
159 } else if (op2 == 0x5) {
160 return new WarnUnimplemented("sel", machInst);
161 }
162 break;
163 case 0x2:
164 if (op2 == 0x1) {
157 return new WarnUnimplemented("ssat16", machInst);
165 const IntRegIndex rn =
166 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
167 const IntRegIndex rd =
168 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
169 const uint32_t satImm = bits(machInst, 20, 16);
170 return new Ssat16(machInst, rd, satImm + 1, rn);
158 } else if (op2 == 0x3) {
159 if (a == 0xf) {
160 return new WarnUnimplemented("sxtb", machInst);
161 } else {
162 return new WarnUnimplemented("sxtab", machInst);
163 }
164 }
165 break;

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186 return new WarnUnimplemented("uxtb16", machInst);
187 } else {
188 return new WarnUnimplemented("uxtab16", machInst);
189 }
190 }
191 break;
192 case 0x6:
193 if (op2 == 0x1) {
171 } else if (op2 == 0x3) {
172 if (a == 0xf) {
173 return new WarnUnimplemented("sxtb", machInst);
174 } else {
175 return new WarnUnimplemented("sxtab", machInst);
176 }
177 }
178 break;

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199 return new WarnUnimplemented("uxtb16", machInst);
200 } else {
201 return new WarnUnimplemented("uxtab16", machInst);
202 }
203 }
204 break;
205 case 0x6:
206 if (op2 == 0x1) {
194 return new WarnUnimplemented("usat16", machInst);
207 const IntRegIndex rn =
208 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
209 const IntRegIndex rd =
210 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
211 const uint32_t satImm = bits(machInst, 20, 16);
212 return new Usat16(machInst, rd, satImm, rn);
195 } else if (op2 == 0x3) {
196 if (a == 0xf) {
197 return new WarnUnimplemented("uxtb", machInst);
198 } else {
199 return new WarnUnimplemented("uxtab", machInst);
200 }
201 }
202 break;

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1103 const uint32_t imm = bits(machInst, 7, 0) |
1104 (bits(machInst, 14, 12) << 8) |
1105 (bits(machInst, 26) << 11) |
1106 (bits(machInst, 19, 16) << 12);
1107 return new MovtImm(machInst, rd, rd, imm, true);
1108 }
1109 case 0x12:
1110 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
213 } else if (op2 == 0x3) {
214 if (a == 0xf) {
215 return new WarnUnimplemented("uxtb", machInst);
216 } else {
217 return new WarnUnimplemented("uxtab", machInst);
218 }
219 }
220 break;

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1121 const uint32_t imm = bits(machInst, 7, 0) |
1122 (bits(machInst, 14, 12) << 8) |
1123 (bits(machInst, 26) << 11) |
1124 (bits(machInst, 19, 16) << 12);
1125 return new MovtImm(machInst, rd, rd, imm, true);
1126 }
1127 case 0x12:
1128 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1111 return new WarnUnimplemented("ssat16", machInst);
1129 const uint32_t satImm = bits(machInst, 4, 0);
1130 return new Ssat16(machInst, rd, satImm + 1, rn);
1112 }
1113 // Fall through on purpose...
1114 case 0x10:
1131 }
1132 // Fall through on purpose...
1133 case 0x10:
1115 return new WarnUnimplemented("ssat", machInst);
1134 {
1135 const uint32_t satImm = bits(machInst, 4, 0);
1136 const uint32_t imm = bits(machInst, 7, 6) |
1137 (bits(machInst, 14, 12) << 2);
1138 const ArmShiftType type =
1139 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1140 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
1141 }
1116 case 0x14:
1117 return new WarnUnimplemented("sbfx", machInst);
1118 case 0x16:
1119 if (rn == 0xf) {
1120 return new WarnUnimplemented("bfc", machInst);
1121 } else {
1122 return new WarnUnimplemented("bfi", machInst);
1123 }
1124 case 0x1a:
1125 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1142 case 0x14:
1143 return new WarnUnimplemented("sbfx", machInst);
1144 case 0x16:
1145 if (rn == 0xf) {
1146 return new WarnUnimplemented("bfc", machInst);
1147 } else {
1148 return new WarnUnimplemented("bfi", machInst);
1149 }
1150 case 0x1a:
1151 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1126 return new WarnUnimplemented("usat16", machInst);
1152 const uint32_t satImm = bits(machInst, 4, 0);
1153 return new Usat16(machInst, rd, satImm, rn);
1127 }
1128 // Fall through on purpose...
1129 case 0x18:
1154 }
1155 // Fall through on purpose...
1156 case 0x18:
1130 return new WarnUnimplemented("usat", machInst);
1157 {
1158 const uint32_t satImm = bits(machInst, 4, 0);
1159 const uint32_t imm = bits(machInst, 7, 6) |
1160 (bits(machInst, 14, 12) << 2);
1161 const ArmShiftType type =
1162 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1163 return new Usat(machInst, rd, satImm, rn, imm, type);
1164 }
1131 case 0x1c:
1132 return new WarnUnimplemented("ubfx", machInst);
1133 default:
1134 return new Unknown(machInst);
1135 }
1136 }
1137 '''
1138}};

--- 94 unchanged lines hidden --- 		1165 case 0x1c:
1166 return new WarnUnimplemented("ubfx", machInst);
1167 default:
1168 return new Unknown(machInst);
1169 }
1170 }
1171 '''
1172}};

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