data.isa (7222:c6c7740edaf3) data.isa (7224:7d22b6d6093f)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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231 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
232 if (bits(machInst, 22) == 0) {
233 switch (op1) {
234 case 0x1:
235 switch (op2) {
236 case 0x0:
237 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
238 case 0x1:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 222 unchanged lines hidden (view full) ---

231 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
232 if (bits(machInst, 22) == 0) {
233 switch (op1) {
234 case 0x1:
235 switch (op2) {
236 case 0x0:
237 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
238 case 0x1:
239 return new WarnUnimplemented("sasx", machInst);
239 return new SasxRegCc(machInst, rd, rn, rm, 0, LSL);
240 case 0x2:
240 case 0x2:
241 return new WarnUnimplemented("ssax", machInst);
241 return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL);
242 case 0x3:
243 return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
244 case 0x4:
245 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
246 case 0x7:
247 return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
248 }
249 break;

--- 298 unchanged lines hidden (view full) ---

548 const uint32_t op2 = bits(machInst, 5, 4);
549 switch (op2) {
550 case 0x0:
551 switch (op1) {
552 case 0x1:
553 return new Sadd16RegCc(machInst, rd,
554 rn, rm, 0, LSL);
555 case 0x2:
242 case 0x3:
243 return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
244 case 0x4:
245 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
246 case 0x7:
247 return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
248 }
249 break;

--- 298 unchanged lines hidden (view full) ---

548 const uint32_t op2 = bits(machInst, 5, 4);
549 switch (op2) {
550 case 0x0:
551 switch (op1) {
552 case 0x1:
553 return new Sadd16RegCc(machInst, rd,
554 rn, rm, 0, LSL);
555 case 0x2:
556 return new WarnUnimplemented("sasx", machInst);
556 return new SasxRegCc(machInst, rd,
557 rn, rm, 0, LSL);
557 case 0x6:
558 case 0x6:
558 return new WarnUnimplemented("ssax", machInst);
559 return new SsaxRegCc(machInst, rd,
560 rn, rm, 0, LSL);
559 case 0x5:
560 return new Ssub16RegCc(machInst, rd,
561 rn, rm, 0, LSL);
562 case 0x0:
563 return new Sadd8RegCc(machInst, rd,
564 rn, rm, 0, LSL);
565 case 0x4:
566 return new Ssub8RegCc(machInst, rd,

--- 664 unchanged lines hidden --- 		561 case 0x5:
562 return new Ssub16RegCc(machInst, rd,
563 rn, rm, 0, LSL);
564 case 0x0:
565 return new Sadd8RegCc(machInst, rd,
566 rn, rm, 0, LSL);
567 case 0x4:
568 return new Ssub8RegCc(machInst, rd,

--- 664 unchanged lines hidden ---