data.isa (7220:31a36c59a937) data.isa (7222:c6c7740edaf3)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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280 }
281 break;
282 }
283 } else {
284 switch (op1) {
285 case 0x1:
286 switch (op2) {
287 case 0x0:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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280 }
281 break;
282 }
283 } else {
284 switch (op1) {
285 case 0x1:
286 switch (op2) {
287 case 0x0:
288 return new WarnUnimplemented("uadd16", machInst);
288 return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL);
289 case 0x1:
289 case 0x1:
290 return new WarnUnimplemented("uasx", machInst);
290 return new UasxRegCc(machInst, rd, rn, rm, 0, LSL);
291 case 0x2:
291 case 0x2:
292 return new WarnUnimplemented("usax", machInst);
292 return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL);
293 case 0x3:
293 case 0x3:
294 return new WarnUnimplemented("usub16", machInst);
294 return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL);
295 case 0x4:
295 case 0x4:
296 return new WarnUnimplemented("uadd8", machInst);
296 return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL);
297 case 0x7:
297 case 0x7:
298 return new WarnUnimplemented("usub8", machInst);
298 return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL);
299 }
300 break;
301 case 0x2:
302 switch (op2) {
303 case 0x0:
304 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
305 case 0x1:
306 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);

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602 }
603 } else {
604 const uint32_t op1 = bits(machInst, 22, 20);
605 const uint32_t op2 = bits(machInst, 5, 4);
606 switch (op2) {
607 case 0x0:
608 switch (op1) {
609 case 0x1:
299 }
300 break;
301 case 0x2:
302 switch (op2) {
303 case 0x0:
304 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
305 case 0x1:
306 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);

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602 }
603 } else {
604 const uint32_t op1 = bits(machInst, 22, 20);
605 const uint32_t op2 = bits(machInst, 5, 4);
606 switch (op2) {
607 case 0x0:
608 switch (op1) {
609 case 0x1:
610 return new WarnUnimplemented("uadd16", machInst);
610 return new Uadd16RegCc(machInst, rd,
611 rn, rm, 0, LSL);
611 case 0x2:
612 case 0x2:
612 return new WarnUnimplemented("uasx", machInst);
613 return new UasxRegCc(machInst, rd,
614 rn, rm, 0, LSL);
613 case 0x6:
615 case 0x6:
614 return new WarnUnimplemented("usax", machInst);
616 return new UsaxRegCc(machInst, rd,
617 rn, rm, 0, LSL);
615 case 0x5:
618 case 0x5:
616 return new WarnUnimplemented("usub16", machInst);
619 return new Usub16RegCc(machInst, rd,
620 rn, rm, 0, LSL);
617 case 0x0:
621 case 0x0:
618 return new WarnUnimplemented("uadd8", machInst);
622 return new Uadd8RegCc(machInst, rd,
623 rn, rm, 0, LSL);
619 case 0x4:
624 case 0x4:
620 return new WarnUnimplemented("usub8", machInst);
625 return new Usub8RegCc(machInst, rd,
626 rn, rm, 0, LSL);
621 }
622 break;
623 case 0x1:
624 switch (op1) {
625 case 0x1:
626 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
627 case 0x2:
628 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);

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628 break;
629 case 0x1:
630 switch (op1) {
631 case 0x1:
632 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
633 case 0x2:
634 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);

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