data.isa (7218:36503d623788) data.isa (7220:31a36c59a937)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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296 return new WarnUnimplemented("uadd8", machInst);
297 case 0x7:
298 return new WarnUnimplemented("usub8", machInst);
299 }
300 break;
301 case 0x2:
302 switch (op2) {
303 case 0x0:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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296 return new WarnUnimplemented("uadd8", machInst);
297 case 0x7:
298 return new WarnUnimplemented("usub8", machInst);
299 }
300 break;
301 case 0x2:
302 switch (op2) {
303 case 0x0:
304 return new WarnUnimplemented("uqadd16", machInst);
304 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
305 case 0x1:
305 case 0x1:
306 return new WarnUnimplemented("uqasx", machInst);
306 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);
307 case 0x2:
307 case 0x2:
308 return new WarnUnimplemented("uqsax", machInst);
308 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL);
309 case 0x3:
309 case 0x3:
310 return new WarnUnimplemented("uqsub16", machInst);
310 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL);
311 case 0x4:
311 case 0x4:
312 return new WarnUnimplemented("uqadd8", machInst);
312 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
313 case 0x7:
313 case 0x7:
314 return new WarnUnimplemented("uqsub8", machInst);
314 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
315 }
316 break;
317 case 0x3:
318 switch (op2) {
319 case 0x0:
320 return new WarnUnimplemented("uhadd16", machInst);
321 case 0x1:
322 return new WarnUnimplemented("uhasx", machInst);

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534 } else {
535 return new WarnUnimplemented("uxtab", machInst);
536 }
537 default:
538 return new Unknown(machInst);
539 }
540 } else {
541 if (bits(op2, 3) == 0) {
315 }
316 break;
317 case 0x3:
318 switch (op2) {
319 case 0x0:
320 return new WarnUnimplemented("uhadd16", machInst);
321 case 0x1:
322 return new WarnUnimplemented("uhasx", machInst);

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534 } else {
535 return new WarnUnimplemented("uxtab", machInst);
536 }
537 default:
538 return new Unknown(machInst);
539 }
540 } else {
541 if (bits(op2, 3) == 0) {
542 const IntRegIndex rd =
543 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
544 const IntRegIndex rm =
545 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
542 if (bits(op2, 2) == 0x0) {
543 const uint32_t op1 = bits(machInst, 22, 20);
544 const uint32_t op2 = bits(machInst, 5, 4);
546 if (bits(op2, 2) == 0x0) {
547 const uint32_t op1 = bits(machInst, 22, 20);
548 const uint32_t op2 = bits(machInst, 5, 4);
545 const IntRegIndex rd =
546 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
547 const IntRegIndex rm =
548 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
549 switch (op2) {
550 case 0x0:
551 switch (op1) {
552 case 0x1:
553 return new Sadd16RegCc(machInst, rd,
554 rn, rm, 0, LSL);
555 case 0x2:
556 return new WarnUnimplemented("sasx", machInst);

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618 return new WarnUnimplemented("uadd8", machInst);
619 case 0x4:
620 return new WarnUnimplemented("usub8", machInst);
621 }
622 break;
623 case 0x1:
624 switch (op1) {
625 case 0x1:
549 switch (op2) {
550 case 0x0:
551 switch (op1) {
552 case 0x1:
553 return new Sadd16RegCc(machInst, rd,
554 rn, rm, 0, LSL);
555 case 0x2:
556 return new WarnUnimplemented("sasx", machInst);

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618 return new WarnUnimplemented("uadd8", machInst);
619 case 0x4:
620 return new WarnUnimplemented("usub8", machInst);
621 }
622 break;
623 case 0x1:
624 switch (op1) {
625 case 0x1:
626 return new WarnUnimplemented("uqadd16", machInst);
626 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
627 case 0x2:
627 case 0x2:
628 return new WarnUnimplemented("uqasx", machInst);
628 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);
629 case 0x6:
629 case 0x6:
630 return new WarnUnimplemented("uqsax", machInst);
630 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL);
631 case 0x5:
631 case 0x5:
632 return new WarnUnimplemented("uqsub16", machInst);
632 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL);
633 case 0x0:
633 case 0x0:
634 return new WarnUnimplemented("uqadd8", machInst);
634 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
635 case 0x4:
635 case 0x4:
636 return new WarnUnimplemented("uqsub8", machInst);
636 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
637 }
638 break;
639 case 0x2:
640 switch (op1) {
641 case 0x1:
642 return new WarnUnimplemented("uhadd16", machInst);
643 case 0x2:
644 return new WarnUnimplemented("uhasx", machInst);

--- 580 unchanged lines hidden --- 		637 }
638 break;
639 case 0x2:
640 switch (op1) {
641 case 0x1:
642 return new WarnUnimplemented("uhadd16", machInst);
643 case 0x2:
644 return new WarnUnimplemented("uhasx", machInst);

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