data.isa (7216:a3261b965224) data.isa (7218:36503d623788)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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235 switch (op2) {
236 case 0x0:
237 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
238 case 0x1:
239 return new WarnUnimplemented("sasx", machInst);
240 case 0x2:
241 return new WarnUnimplemented("ssax", machInst);
242 case 0x3:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 226 unchanged lines hidden (view full) ---

235 switch (op2) {
236 case 0x0:
237 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
238 case 0x1:
239 return new WarnUnimplemented("sasx", machInst);
240 case 0x2:
241 return new WarnUnimplemented("ssax", machInst);
242 case 0x3:
243 return new WarnUnimplemented("ssub16", machInst);
243 return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
244 case 0x4:
245 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
246 case 0x7:
244 case 0x4:
245 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
246 case 0x7:
247 return new WarnUnimplemented("ssub8", machInst);
247 return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
248 }
249 break;
250 case 0x2:
251 switch (op2) {
252 case 0x0:
253 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
254 case 0x1:
255 return new QasxReg(machInst, rd, rn, rm, 0, LSL);

--- 296 unchanged lines hidden (view full) ---

552 case 0x1:
553 return new Sadd16RegCc(machInst, rd,
554 rn, rm, 0, LSL);
555 case 0x2:
556 return new WarnUnimplemented("sasx", machInst);
557 case 0x6:
558 return new WarnUnimplemented("ssax", machInst);
559 case 0x5:
248 }
249 break;
250 case 0x2:
251 switch (op2) {
252 case 0x0:
253 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
254 case 0x1:
255 return new QasxReg(machInst, rd, rn, rm, 0, LSL);

--- 296 unchanged lines hidden (view full) ---

552 case 0x1:
553 return new Sadd16RegCc(machInst, rd,
554 rn, rm, 0, LSL);
555 case 0x2:
556 return new WarnUnimplemented("sasx", machInst);
557 case 0x6:
558 return new WarnUnimplemented("ssax", machInst);
559 case 0x5:
560 return new WarnUnimplemented("ssub16", machInst);
560 return new Ssub16RegCc(machInst, rd,
561 rn, rm, 0, LSL);
561 case 0x0:
562 return new Sadd8RegCc(machInst, rd,
563 rn, rm, 0, LSL);
564 case 0x4:
562 case 0x0:
563 return new Sadd8RegCc(machInst, rd,
564 rn, rm, 0, LSL);
565 case 0x4:
565 return new WarnUnimplemented("ssub8", machInst);
566 return new Ssub8RegCc(machInst, rd,
567 rn, rm, 0, LSL);
566 }
567 break;
568 case 0x1:
569 switch (op1) {
570 case 0x1:
571 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
572 case 0x2:
573 return new QasxReg(machInst, rd, rn, rm, 0, LSL);

--- 649 unchanged lines hidden --- 		568 }
569 break;
570 case 0x1:
571 switch (op1) {
572 case 0x1:
573 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
574 case 0x2:
575 return new QasxReg(machInst, rd, rn, rm, 0, LSL);

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