data.isa (7213:beadb1dc1be6) data.isa (7216:a3261b965224)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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229 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
230 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
231 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
232 if (bits(machInst, 22) == 0) {
233 switch (op1) {
234 case 0x1:
235 switch (op2) {
236 case 0x0:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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229 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
230 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
231 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
232 if (bits(machInst, 22) == 0) {
233 switch (op1) {
234 case 0x1:
235 switch (op2) {
236 case 0x0:
237 return new WarnUnimplemented("sadd16", machInst);
237 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
238 case 0x1:
239 return new WarnUnimplemented("sasx", machInst);
240 case 0x2:
241 return new WarnUnimplemented("ssax", machInst);
242 case 0x3:
243 return new WarnUnimplemented("ssub16", machInst);
244 case 0x4:
238 case 0x1:
239 return new WarnUnimplemented("sasx", machInst);
240 case 0x2:
241 return new WarnUnimplemented("ssax", machInst);
242 case 0x3:
243 return new WarnUnimplemented("ssub16", machInst);
244 case 0x4:
245 return new WarnUnimplemented("sadd8", machInst);
245 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
246 case 0x7:
247 return new WarnUnimplemented("ssub8", machInst);
248 }
249 break;
250 case 0x2:
251 switch (op2) {
252 case 0x0:
253 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);

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537 default:
538 return new Unknown(machInst);
539 }
540 } else {
541 if (bits(op2, 3) == 0) {
542 if (bits(op2, 2) == 0x0) {
543 const uint32_t op1 = bits(machInst, 22, 20);
544 const uint32_t op2 = bits(machInst, 5, 4);
246 case 0x7:
247 return new WarnUnimplemented("ssub8", machInst);
248 }
249 break;
250 case 0x2:
251 switch (op2) {
252 case 0x0:
253 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);

--- 283 unchanged lines hidden (view full) ---

537 default:
538 return new Unknown(machInst);
539 }
540 } else {
541 if (bits(op2, 3) == 0) {
542 if (bits(op2, 2) == 0x0) {
543 const uint32_t op1 = bits(machInst, 22, 20);
544 const uint32_t op2 = bits(machInst, 5, 4);
545 const IntRegIndex rd =
546 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
547 const IntRegIndex rm =
548 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
545 switch (op2) {
546 case 0x0:
547 switch (op1) {
548 case 0x1:
549 switch (op2) {
550 case 0x0:
551 switch (op1) {
552 case 0x1:
549 return new WarnUnimplemented("sadd16", machInst);
553 return new Sadd16RegCc(machInst, rd,
554 rn, rm, 0, LSL);
550 case 0x2:
551 return new WarnUnimplemented("sasx", machInst);
552 case 0x6:
553 return new WarnUnimplemented("ssax", machInst);
554 case 0x5:
555 return new WarnUnimplemented("ssub16", machInst);
556 case 0x0:
555 case 0x2:
556 return new WarnUnimplemented("sasx", machInst);
557 case 0x6:
558 return new WarnUnimplemented("ssax", machInst);
559 case 0x5:
560 return new WarnUnimplemented("ssub16", machInst);
561 case 0x0:
557 return new WarnUnimplemented("sadd8", machInst);
562 return new Sadd8RegCc(machInst, rd,
563 rn, rm, 0, LSL);
558 case 0x4:
559 return new WarnUnimplemented("ssub8", machInst);
560 }
561 break;
562 case 0x1:
564 case 0x4:
565 return new WarnUnimplemented("ssub8", machInst);
566 }
567 break;
568 case 0x1:
563 {
564 IntRegIndex rn =
565 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
566 IntRegIndex rd =
567 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
568 IntRegIndex rm =
569 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
570 switch (op1) {
571 case 0x1:
572 return new Qadd16Reg(machInst, rd,
573 rn, rm, 0, LSL);
574 case 0x2:
575 return new QasxReg(machInst, rd,
576 rn, rm, 0, LSL);
577 case 0x6:
578 return new QsaxReg(machInst, rd,
579 rn, rm, 0, LSL);
580 case 0x5:
581 return new Qsub16Reg(machInst, rd,
582 rn, rm, 0, LSL);
583 case 0x0:
584 return new Qsub8Reg(machInst, rd,
585 rn, rm, 0, LSL);
586 case 0x4:
587 return new Qsub8Reg(machInst, rd,
588 rn, rm, 0, LSL);
589 }
569 switch (op1) {
570 case 0x1:
571 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
572 case 0x2:
573 return new QasxReg(machInst, rd, rn, rm, 0, LSL);
574 case 0x6:
575 return new QsaxReg(machInst, rd, rn, rm, 0, LSL);
576 case 0x5:
577 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL);
578 case 0x0:
579 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
580 case 0x4:
581 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
590 }
591 break;
592 case 0x2:
593 switch (op1) {
594 case 0x1:
595 return new WarnUnimplemented("shadd16", machInst);
596 case 0x2:
597 return new WarnUnimplemented("shasx", machInst);

--- 633 unchanged lines hidden --- 		582 }
583 break;
584 case 0x2:
585 switch (op1) {
586 case 0x1:
587 return new WarnUnimplemented("shadd16", machInst);
588 case 0x2:
589 return new WarnUnimplemented("shasx", machInst);

--- 633 unchanged lines hidden ---