data.isa (7212:746657ee59a2) data.isa (7213:beadb1dc1be6)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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455 return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
456 default:
457 return new Unknown(machInst);
458 }
459 }
460 '''
461}};
462
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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455 return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
456 default:
457 return new Unknown(machInst);
458 }
459 }
460 '''
461}};
462
463def format Thumb32DataProcReg() {{
464 decode_block = '''
465 {
466 const uint32_t op1 = bits(machInst, 23, 20);
467 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
468 const uint32_t op2 = bits(machInst, 7, 4);
469 if (bits(op1, 3) != 1) {
470 if (op2 == 0) {
471 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
472 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
473 switch (bits(op1, 2, 0)) {
474 case 0x0:
475 return new MovRegReg(machInst, rd,
476 INTREG_ZERO, rn, rm, LSL);
477 case 0x1:
478 return new MovRegRegCc(machInst, rd,
479 INTREG_ZERO, rn, rm, LSL);
480 case 0x2:
481 return new MovRegReg(machInst, rd,
482 INTREG_ZERO, rn, rm, LSR);
483 case 0x3:
484 return new MovRegRegCc(machInst, rd,
485 INTREG_ZERO, rn, rm, LSR);
486 case 0x4:
487 return new MovRegReg(machInst, rd,
488 INTREG_ZERO, rn, rm, ASR);
489 case 0x5:
490 return new MovRegRegCc(machInst, rd,
491 INTREG_ZERO, rn, rm, ASR);
492 case 0x6:
493 return new MovRegReg(machInst, rd,
494 INTREG_ZERO, rn, rm, ROR);
495 case 0x7:
496 return new MovRegRegCc(machInst, rd,
497 INTREG_ZERO, rn, rm, ROR);
498 }
499 }
500 switch (bits(op1, 2, 0)) {
501 case 0x0:
502 if (rn == 0xf) {
503 return new WarnUnimplemented("sxth", machInst);
504 } else {
505 return new WarnUnimplemented("sxtah", machInst);
506 }
507 case 0x1:
508 if (rn == 0xf) {
509 return new WarnUnimplemented("uxth", machInst);
510 } else {
511 return new WarnUnimplemented("uxtah", machInst);
512 }
513 case 0x2:
514 if (rn == 0xf) {
515 return new WarnUnimplemented("sxtb16", machInst);
516 } else {
517 return new WarnUnimplemented("sxtab16", machInst);
518 }
519 case 0x3:
520 if (rn == 0xf) {
521 return new WarnUnimplemented("uxtb16", machInst);
522 } else {
523 return new WarnUnimplemented("uxtab16", machInst);
524 }
525 case 0x4:
526 if (rn == 0xf) {
527 return new WarnUnimplemented("sxtb", machInst);
528 } else {
529 return new WarnUnimplemented("sxtab", machInst);
530 }
531 case 0x5:
532 if (rn == 0xf) {
533 return new WarnUnimplemented("uxtb", machInst);
534 } else {
535 return new WarnUnimplemented("uxtab", machInst);
536 }
537 default:
538 return new Unknown(machInst);
539 }
540 } else {
541 if (bits(op2, 3) == 0) {
542 if (bits(op2, 2) == 0x0) {
543 const uint32_t op1 = bits(machInst, 22, 20);
544 const uint32_t op2 = bits(machInst, 5, 4);
545 switch (op2) {
546 case 0x0:
547 switch (op1) {
548 case 0x1:
549 return new WarnUnimplemented("sadd16", machInst);
550 case 0x2:
551 return new WarnUnimplemented("sasx", machInst);
552 case 0x6:
553 return new WarnUnimplemented("ssax", machInst);
554 case 0x5:
555 return new WarnUnimplemented("ssub16", machInst);
556 case 0x0:
557 return new WarnUnimplemented("sadd8", machInst);
558 case 0x4:
559 return new WarnUnimplemented("ssub8", machInst);
560 }
561 break;
562 case 0x1:
563 {
564 IntRegIndex rn =
565 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
566 IntRegIndex rd =
567 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
568 IntRegIndex rm =
569 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
570 switch (op1) {
571 case 0x1:
572 return new Qadd16Reg(machInst, rd,
573 rn, rm, 0, LSL);
574 case 0x2:
575 return new QasxReg(machInst, rd,
576 rn, rm, 0, LSL);
577 case 0x6:
578 return new QsaxReg(machInst, rd,
579 rn, rm, 0, LSL);
580 case 0x5:
581 return new Qsub16Reg(machInst, rd,
582 rn, rm, 0, LSL);
583 case 0x0:
584 return new Qsub8Reg(machInst, rd,
585 rn, rm, 0, LSL);
586 case 0x4:
587 return new Qsub8Reg(machInst, rd,
588 rn, rm, 0, LSL);
589 }
590 }
591 break;
592 case 0x2:
593 switch (op1) {
594 case 0x1:
595 return new WarnUnimplemented("shadd16", machInst);
596 case 0x2:
597 return new WarnUnimplemented("shasx", machInst);
598 case 0x6:
599 return new WarnUnimplemented("shsax", machInst);
600 case 0x5:
601 return new WarnUnimplemented("shsub16", machInst);
602 case 0x0:
603 return new WarnUnimplemented("shadd8", machInst);
604 case 0x4:
605 return new WarnUnimplemented("shsub8", machInst);
606 }
607 break;
608 }
609 } else {
610 const uint32_t op1 = bits(machInst, 22, 20);
611 const uint32_t op2 = bits(machInst, 5, 4);
612 switch (op2) {
613 case 0x0:
614 switch (op1) {
615 case 0x1:
616 return new WarnUnimplemented("uadd16", machInst);
617 case 0x2:
618 return new WarnUnimplemented("uasx", machInst);
619 case 0x6:
620 return new WarnUnimplemented("usax", machInst);
621 case 0x5:
622 return new WarnUnimplemented("usub16", machInst);
623 case 0x0:
624 return new WarnUnimplemented("uadd8", machInst);
625 case 0x4:
626 return new WarnUnimplemented("usub8", machInst);
627 }
628 break;
629 case 0x1:
630 switch (op1) {
631 case 0x1:
632 return new WarnUnimplemented("uqadd16", machInst);
633 case 0x2:
634 return new WarnUnimplemented("uqasx", machInst);
635 case 0x6:
636 return new WarnUnimplemented("uqsax", machInst);
637 case 0x5:
638 return new WarnUnimplemented("uqsub16", machInst);
639 case 0x0:
640 return new WarnUnimplemented("uqadd8", machInst);
641 case 0x4:
642 return new WarnUnimplemented("uqsub8", machInst);
643 }
644 break;
645 case 0x2:
646 switch (op1) {
647 case 0x1:
648 return new WarnUnimplemented("uhadd16", machInst);
649 case 0x2:
650 return new WarnUnimplemented("uhasx", machInst);
651 case 0x6:
652 return new WarnUnimplemented("uhsax", machInst);
653 case 0x5:
654 return new WarnUnimplemented("uhsub16", machInst);
655 case 0x0:
656 return new WarnUnimplemented("uhadd8", machInst);
657 case 0x4:
658 return new WarnUnimplemented("uhsub8", machInst);
659 }
660 break;
661 }
662 }
663 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) {
664 const uint32_t op1 = bits(machInst, 21, 20);
665 const uint32_t op2 = bits(machInst, 5, 4);
666 switch (op1) {
667 case 0x0:
668 {
669 IntRegIndex rd =
670 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
671 IntRegIndex rm =
672 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
673 switch (op2) {
674 case 0x0:
675 return new QaddRegCc(machInst, rd,
676 rm, rn, 0, LSL);
677 case 0x1:
678 return new QdaddRegCc(machInst, rd,
679 rm, rn, 0, LSL);
680 case 0x2:
681 return new QsubRegCc(machInst, rd,
682 rm, rn, 0, LSL);
683 case 0x3:
684 return new QdsubRegCc(machInst, rd,
685 rm, rn, 0, LSL);
686 }
687 }
688 break;
689 case 0x1:
690 {
691 IntRegIndex rd =
692 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
693 IntRegIndex rm = rn;
694 switch (op2) {
695 case 0x0:
696 return new Rev(machInst, rd, rm);
697 case 0x1:
698 return new Rev16(machInst, rd, rm);
699 case 0x2:
700 return new WarnUnimplemented("rbit", machInst);
701 case 0x3:
702 return new Revsh(machInst, rd, rm);
703 }
704 }
705 break;
706 case 0x2:
707 if (op2 == 0) {
708 return new WarnUnimplemented("sel", machInst);
709 }
710 break;
711 case 0x3:
712 if (op2 == 0) {
713 return new WarnUnimplemented("clz", machInst);
714 }
715 }
716 }
717 return new Unknown(machInst);
718 }
719 }
720 '''
721}};
722
463def format Thumb16ShiftAddSubMoveCmp() {{
464 decode_block = '''
465 {
466 const uint32_t imm5 = bits(machInst, 10, 6);
467 const uint32_t imm3 = bits(machInst, 8, 6);
468 const uint32_t imm8 = bits(machInst, 7, 0);
469 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
470 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);

--- 500 unchanged lines hidden --- 		723def format Thumb16ShiftAddSubMoveCmp() {{
724 decode_block = '''
725 {
726 const uint32_t imm5 = bits(machInst, 10, 6);
727 const uint32_t imm3 = bits(machInst, 8, 6);
728 const uint32_t imm8 = bits(machInst, 7, 0);
729 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
730 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);

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