data.isa (7210:10d2d0e1e39d) data.isa (7211:34f55e88891c)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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160 return new WarnUnimplemented("sxtb", machInst);
161 } else {
162 return new WarnUnimplemented("sxtab", machInst);
163 }
164 }
165 break;
166 case 0x3:
167 if (op2 == 0x1) {
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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160 return new WarnUnimplemented("sxtb", machInst);
161 } else {
162 return new WarnUnimplemented("sxtab", machInst);
163 }
164 }
165 break;
166 case 0x3:
167 if (op2 == 0x1) {
168 return new WarnUnimplemented("rev", machInst);
168 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
169 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
170 return new Rev(machInst, rd, rm);
169 } else if (op2 == 0x3) {
170 if (a == 0xf) {
171 return new WarnUnimplemented("sxth", machInst);
172 } else {
173 return new WarnUnimplemented("sxtah", machInst);
174 }
175 } else if (op2 == 0x5) {
171 } else if (op2 == 0x3) {
172 if (a == 0xf) {
173 return new WarnUnimplemented("sxth", machInst);
174 } else {
175 return new WarnUnimplemented("sxtah", machInst);
176 }
177 } else if (op2 == 0x5) {
176 return new WarnUnimplemented("rev16", machInst);
178 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
179 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
180 return new Rev16(machInst, rd, rm);
177 }
178 break;
179 case 0x4:
180 if (op2 == 0x3) {
181 if (a == 0xf) {
182 return new WarnUnimplemented("uxtb16", machInst);
183 } else {
184 return new WarnUnimplemented("uxtab16", machInst);

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201 return new WarnUnimplemented("rbit", machInst);
202 } else if (op2 == 0x3) {
203 if (a == 0xf) {
204 return new WarnUnimplemented("uxth", machInst);
205 } else {
206 return new WarnUnimplemented("uxtah", machInst);
207 }
208 } else if (op2 == 0x5) {
181 }
182 break;
183 case 0x4:
184 if (op2 == 0x3) {
185 if (a == 0xf) {
186 return new WarnUnimplemented("uxtb16", machInst);
187 } else {
188 return new WarnUnimplemented("uxtab16", machInst);

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205 return new WarnUnimplemented("rbit", machInst);
206 } else if (op2 == 0x3) {
207 if (a == 0xf) {
208 return new WarnUnimplemented("uxth", machInst);
209 } else {
210 return new WarnUnimplemented("uxtah", machInst);
211 }
212 } else if (op2 == 0x5) {
209 return new WarnUnimplemented("revsh", machInst);
213 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
214 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
215 return new Revsh(machInst, rd, rm);
210 }
211 break;
212 }
213 return new Unknown(machInst);
214 }
215 '''
216}};
217

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217 break;
218 }
219 return new Unknown(machInst);
220 }
221 '''
222}};
223

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