data.isa (7201:253d16049184) data.isa (7210:10d2d0e1e39d)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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119 decode_block += '''
120 default:
121 return new Unknown(machInst);
122 }
123 }
124 '''
125}};
126
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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119 decode_block += '''
120 default:
121 return new Unknown(machInst);
122 }
123 }
124 '''
125}};
126
127def format ArmPackUnpackSatReverse() {{
128 decode_block = '''
129 {
130 const uint32_t op1 = bits(machInst, 22, 20);
131 const uint32_t a = bits(machInst, 19, 16);
132 const uint32_t op2 = bits(machInst, 7, 5);
133 if (bits(op2, 0) == 0) {
134 if (op1 == 0) {
135 return new WarnUnimplemented("pkh", machInst);
136 } else if (bits(op1, 2, 1) == 1) {
137 return new WarnUnimplemented("ssat", machInst);
138 } else if (bits(op1, 2, 1) == 3) {
139 return new WarnUnimplemented("usat", machInst);
140 }
141 return new Unknown(machInst);
142 }
143 switch (op1) {
144 case 0x0:
145 if (op2 == 0x3) {
146 if (a == 0xf) {
147 return new WarnUnimplemented("sxtb16", machInst);
148 } else {
149 return new WarnUnimplemented("sxtab16", machInst);
150 }
151 } else if (op2 == 0x5) {
152 return new WarnUnimplemented("sel", machInst);
153 }
154 break;
155 case 0x2:
156 if (op2 == 0x1) {
157 return new WarnUnimplemented("ssat16", machInst);
158 } else if (op2 == 0x3) {
159 if (a == 0xf) {
160 return new WarnUnimplemented("sxtb", machInst);
161 } else {
162 return new WarnUnimplemented("sxtab", machInst);
163 }
164 }
165 break;
166 case 0x3:
167 if (op2 == 0x1) {
168 return new WarnUnimplemented("rev", machInst);
169 } else if (op2 == 0x3) {
170 if (a == 0xf) {
171 return new WarnUnimplemented("sxth", machInst);
172 } else {
173 return new WarnUnimplemented("sxtah", machInst);
174 }
175 } else if (op2 == 0x5) {
176 return new WarnUnimplemented("rev16", machInst);
177 }
178 break;
179 case 0x4:
180 if (op2 == 0x3) {
181 if (a == 0xf) {
182 return new WarnUnimplemented("uxtb16", machInst);
183 } else {
184 return new WarnUnimplemented("uxtab16", machInst);
185 }
186 }
187 break;
188 case 0x6:
189 if (op2 == 0x1) {
190 return new WarnUnimplemented("usat16", machInst);
191 } else if (op2 == 0x3) {
192 if (a == 0xf) {
193 return new WarnUnimplemented("uxtb", machInst);
194 } else {
195 return new WarnUnimplemented("uxtab", machInst);
196 }
197 }
198 break;
199 case 0x7:
200 if (op2 == 0x1) {
201 return new WarnUnimplemented("rbit", machInst);
202 } else if (op2 == 0x3) {
203 if (a == 0xf) {
204 return new WarnUnimplemented("uxth", machInst);
205 } else {
206 return new WarnUnimplemented("uxtah", machInst);
207 }
208 } else if (op2 == 0x5) {
209 return new WarnUnimplemented("revsh", machInst);
210 }
211 break;
212 }
213 return new Unknown(machInst);
214 }
215 '''
216}};
217
127def format ArmParallelAddSubtract() {{
128 decode_block='''
129 {
130 const uint32_t op1 = bits(machInst, 21, 20);
131 const uint32_t op2 = bits(machInst, 7, 5);
132 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
133 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
134 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);

--- 735 unchanged lines hidden --- 		218def format ArmParallelAddSubtract() {{
219 decode_block='''
220 {
221 const uint32_t op1 = bits(machInst, 21, 20);
222 const uint32_t op2 = bits(machInst, 7, 5);
223 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
224 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
225 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);

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