data.isa (7188:1310866e4ed5) data.isa (7194:f72dc8789553)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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119 decode_block += '''
120 default:
121 return new Unknown(machInst);
122 }
123 }
124 '''
125}};
126
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 110 unchanged lines hidden (view full) ---

119 decode_block += '''
120 default:
121 return new Unknown(machInst);
122 }
123 }
124 '''
125}};
126
127def format ArmParallelAddSubtract() {{
128 decode_block='''
129 {
130 const uint32_t op1 = bits(machInst, 21, 20);
131 const uint32_t op2 = bits(machInst, 7, 5);
132 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
133 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
134 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
135 if (bits(machInst, 22) == 0) {
136 switch (op1) {
137 case 0x1:
138 switch (op2) {
139 case 0x0:
140 return new WarnUnimplemented("sadd16", machInst);
141 case 0x1:
142 return new WarnUnimplemented("sasx", machInst);
143 case 0x2:
144 return new WarnUnimplemented("ssax", machInst);
145 case 0x3:
146 return new WarnUnimplemented("ssub16", machInst);
147 case 0x4:
148 return new WarnUnimplemented("sadd8", machInst);
149 case 0x7:
150 return new WarnUnimplemented("ssub8", machInst);
151 }
152 break;
153 case 0x2:
154 switch (op2) {
155 case 0x0:
156 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
157 case 0x1:
158 return new QasxReg(machInst, rd, rn, rm, 0, LSL);
159 case 0x2:
160 return new QsaxReg(machInst, rd, rn, rm, 0, LSL);
161 case 0x3:
162 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL);
163 case 0x4:
164 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
165 case 0x7:
166 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
167 }
168 break;
169 case 0x3:
170 switch (op2) {
171 case 0x0:
172 return new WarnUnimplemented("shadd16", machInst);
173 case 0x1:
174 return new WarnUnimplemented("shasx", machInst);
175 case 0x2:
176 return new WarnUnimplemented("shsax", machInst);
177 case 0x3:
178 return new WarnUnimplemented("shsub16", machInst);
179 case 0x4:
180 return new WarnUnimplemented("shadd8", machInst);
181 case 0x7:
182 return new WarnUnimplemented("shsub8", machInst);
183 }
184 break;
185 }
186 } else {
187 switch (op1) {
188 case 0x1:
189 switch (op2) {
190 case 0x0:
191 return new WarnUnimplemented("uadd16", machInst);
192 case 0x1:
193 return new WarnUnimplemented("uasx", machInst);
194 case 0x2:
195 return new WarnUnimplemented("usax", machInst);
196 case 0x3:
197 return new WarnUnimplemented("usub16", machInst);
198 case 0x4:
199 return new WarnUnimplemented("uadd8", machInst);
200 case 0x7:
201 return new WarnUnimplemented("usub8", machInst);
202 }
203 break;
204 case 0x2:
205 switch (op2) {
206 case 0x0:
207 return new WarnUnimplemented("uqadd16", machInst);
208 case 0x1:
209 return new WarnUnimplemented("uqasx", machInst);
210 case 0x2:
211 return new WarnUnimplemented("uqsax", machInst);
212 case 0x3:
213 return new WarnUnimplemented("uqsub16", machInst);
214 case 0x4:
215 return new WarnUnimplemented("uqadd8", machInst);
216 case 0x7:
217 return new WarnUnimplemented("uqsub8", machInst);
218 }
219 break;
220 case 0x3:
221 switch (op2) {
222 case 0x0:
223 return new WarnUnimplemented("uhadd16", machInst);
224 case 0x1:
225 return new WarnUnimplemented("uhasx", machInst);
226 case 0x2:
227 return new WarnUnimplemented("uhsax", machInst);
228 case 0x3:
229 return new WarnUnimplemented("uhsub16", machInst);
230 case 0x4:
231 return new WarnUnimplemented("uhadd8", machInst);
232 case 0x7:
233 return new WarnUnimplemented("uhsub8", machInst);
234 }
235 break;
236 }
237 }
238 return new Unknown(machInst);
239 }
240 '''
241}};
242
127def format ArmDataProcImm() {{
128 pclr = '''
129 return new %(className)ssImmPclr(machInst, %(dest)s,
130 %(op1)s, imm, false);
131 '''
132 adr = '''
133 return new AdrImm(machInst, %(dest)s, %(add)s,
134 imm, false);

--- 587 unchanged lines hidden --- 		243def format ArmDataProcImm() {{
244 pclr = '''
245 return new %(className)ssImmPclr(machInst, %(dest)s,
246 %(op1)s, imm, false);
247 '''
248 adr = '''
249 return new AdrImm(machInst, %(dest)s, %(add)s,
250 imm, false);

--- 587 unchanged lines hidden ---