data.isa (7183:e02a07983705) data.isa (7185:13467caed8e1)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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98 return new Unknown(machInst);
99 }
100 }
101 '''
102}};
103
104def format ArmDataProcImm() {{
105 instDecode = '''
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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98 return new Unknown(machInst);
99 }
100 }
101 '''
102}};
103
104def format ArmDataProcImm() {{
105 instDecode = '''
106 case %(opcode)#x:
107 if (setCc) {
108 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
109 imm, rotC);
110 } else {
111 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
112 imm, rotC);
113 }
114 break;
115 '''
116
117 def instCode(opcode, mnem, dest="rd", op1="rn"):
118 global instDecode
106 if (setCc) {
107 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
108 imm, rotC);
109 } else {
110 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
111 imm, rotC);
112 }
113 break;
114 '''
115
116 def instCode(opcode, mnem, dest="rd", op1="rn"):
117 global instDecode
119 return instDecode % { "className": mnem.capitalize(),
120 "opcode": opcode,
121 "dest": dest,
122 "op1": op1 }
118 code = '''
119 case %(opcode)#x:
120 ''' + instDecode
121 return code % { "className": mnem.capitalize(),
122 "opcode": opcode,
123 "dest": dest,
124 "op1": op1 }
123
125
126 def adrCode(opcode, mnem, dest="rd", op1="rn", add="1"):
127 global instDecode
128 code = '''
129 case %(opcode)#x:
130 if (rn == 0xf) {
131 return new AdrImm(machInst, %(dest)s, %(add)s,
132 imm, false);
133 } else {
134 ''' + instDecode + '''
135 }
136 '''
137 return code % { "className": mnem.capitalize(),
138 "opcode": opcode,
139 "dest": dest,
140 "add": add,
141 "op1": op1 }
142
124 decode_block = '''
125 {
126 const bool setCc = (bits(machInst, 20) == 1);
127 const uint32_t unrotated = bits(machInst, 7, 0);
128 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
129 const bool rotC = (rotation != 0);
130 const uint32_t imm = rotate_imm(unrotated, rotation);
131 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
132 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
133 switch (OPCODE) {
134 '''
135 decode_block += instCode(0x0, "and")
136 decode_block += instCode(0x1, "eor")
143 decode_block = '''
144 {
145 const bool setCc = (bits(machInst, 20) == 1);
146 const uint32_t unrotated = bits(machInst, 7, 0);
147 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
148 const bool rotC = (rotation != 0);
149 const uint32_t imm = rotate_imm(unrotated, rotation);
150 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
151 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
152 switch (OPCODE) {
153 '''
154 decode_block += instCode(0x0, "and")
155 decode_block += instCode(0x1, "eor")
137 decode_block += instCode(0x2, "sub")
156 decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0")
138 decode_block += instCode(0x3, "rsb")
157 decode_block += instCode(0x3, "rsb")
139 decode_block += instCode(0x4, "add")
158 decode_block += adrCode(0x4, "add", add="(IntRegIndex)1")
140 decode_block += instCode(0x5, "adc")
141 decode_block += instCode(0x6, "sbc")
142 decode_block += instCode(0x7, "rsc")
143 decode_block += instCode(0x8, "tst", dest="INTREG_ZERO")
144 decode_block += instCode(0x9, "teq", dest="INTREG_ZERO")
145 decode_block += instCode(0xa, "cmp", dest="INTREG_ZERO")
146 decode_block += instCode(0xb, "cmn", dest="INTREG_ZERO")
147 decode_block += instCode(0xc, "orr")

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269 '''
270}};
271
272def format Thumb16Adr() {{
273 decode_block = '''
274 {
275 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
276 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
159 decode_block += instCode(0x5, "adc")
160 decode_block += instCode(0x6, "sbc")
161 decode_block += instCode(0x7, "rsc")
162 decode_block += instCode(0x8, "tst", dest="INTREG_ZERO")
163 decode_block += instCode(0x9, "teq", dest="INTREG_ZERO")
164 decode_block += instCode(0xa, "cmp", dest="INTREG_ZERO")
165 decode_block += instCode(0xb, "cmn", dest="INTREG_ZERO")
166 decode_block += instCode(0xc, "orr")

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288 '''
289}};
290
291def format Thumb16Adr() {{
292 decode_block = '''
293 {
294 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
295 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
277 return new AddImm(machInst, rd, INTREG_PC, imm8, true);
296 return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false);
278 }
279 '''
280}};
281
282def format Thumb16AddSp() {{
283 decode_block = '''
284 {
285 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);

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486 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
487 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
488 switch (op) {
489 case 0x0:
490 {
491 const uint32_t imm = bits(machInst, 7, 0) |
492 (bits(machInst, 14, 12) << 8) |
493 (bits(machInst, 26) << 11);
297 }
298 '''
299}};
300
301def format Thumb16AddSp() {{
302 decode_block = '''
303 {
304 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);

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505 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
506 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
507 switch (op) {
508 case 0x0:
509 {
510 const uint32_t imm = bits(machInst, 7, 0) |
511 (bits(machInst, 14, 12) << 8) |
512 (bits(machInst, 26) << 11);
494 return new AddImm(machInst, rd, rn, imm, true);
513 if (rn == 0xf) {
514 return new AdrImm(machInst, rd, (IntRegIndex)1,
515 imm, false);
516 } else {
517 return new AddImm(machInst, rd, rn, imm, true);
518 }
495 }
496 case 0x4:
497 {
498 const uint32_t imm = bits(machInst, 7, 0) |
499 (bits(machInst, 14, 12) << 8) |
500 (bits(machInst, 26) << 11) |
501 (bits(machInst, 19, 16) << 12);
502 return new MovImm(machInst, rd, INTREG_ZERO, imm, true);
503 }
504 case 0xa:
505 {
506 const uint32_t imm = bits(machInst, 7, 0) |
507 (bits(machInst, 14, 12) << 8) |
508 (bits(machInst, 26) << 11);
519 }
520 case 0x4:
521 {
522 const uint32_t imm = bits(machInst, 7, 0) |
523 (bits(machInst, 14, 12) << 8) |
524 (bits(machInst, 26) << 11) |
525 (bits(machInst, 19, 16) << 12);
526 return new MovImm(machInst, rd, INTREG_ZERO, imm, true);
527 }
528 case 0xa:
529 {
530 const uint32_t imm = bits(machInst, 7, 0) |
531 (bits(machInst, 14, 12) << 8) |
532 (bits(machInst, 26) << 11);
509 return new SubImm(machInst, rd, rn, imm, true);
533 if (rn == 0xf) {
534 return new AdrImm(machInst, rd, (IntRegIndex)0,
535 imm, false);
536 } else {
537 return new SubImm(machInst, rd, rn, imm, true);
538 }
510 }
511 case 0xc:
512 {
513 const uint32_t imm = bits(machInst, 7, 0) |
514 (bits(machInst, 14, 12) << 8) |
515 (bits(machInst, 26) << 11) |
516 (bits(machInst, 19, 16) << 12);
517 return new MovtImm(machInst, rd, rd, imm, true);

--- 125 unchanged lines hidden --- 		539 }
540 case 0xc:
541 {
542 const uint32_t imm = bits(machInst, 7, 0) |
543 (bits(machInst, 14, 12) << 8) |
544 (bits(machInst, 26) << 11) |
545 (bits(machInst, 19, 16) << 12);
546 return new MovtImm(machInst, rd, rd, imm, true);

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