data.isa (7162:97fe2d298f3e) data.isa (7183:e02a07983705)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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163 const uint32_t imm3 = bits(machInst, 8, 6);
164 const uint32_t imm8 = bits(machInst, 7, 0);
165 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
166 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
167 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
168 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
169 switch (bits(machInst, 13, 11)) {
170 case 0x0: // lsl
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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163 const uint32_t imm3 = bits(machInst, 8, 6);
164 const uint32_t imm8 = bits(machInst, 7, 0);
165 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
166 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
167 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
168 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
169 switch (bits(machInst, 13, 11)) {
170 case 0x0: // lsl
171 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
171 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
172 case 0x1: // lsr
172 case 0x1: // lsr
173 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
173 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
174 case 0x2: // asr
174 case 0x2: // asr
175 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
175 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
176 case 0x3:
177 switch (bits(machInst, 10, 9)) {
178 case 0x0:
176 case 0x3:
177 switch (bits(machInst, 10, 9)) {
178 case 0x0:
179 return new AddReg(machInst, rd, rn, rm, 0, LSL);
179 return new AddRegCc(machInst, rd, rn, rm, 0, LSL);
180 case 0x1:
180 case 0x1:
181 return new SubReg(machInst, rd, rn, rm, 0, LSL);
181 return new SubRegCc(machInst, rd, rn, rm, 0, LSL);
182 case 0x2:
182 case 0x2:
183 return new AddImm(machInst, rd, rn, imm3, true);
183 return new AddImmCc(machInst, rd, rn, imm3, true);
184 case 0x3:
184 case 0x3:
185 return new SubImm(machInst, rd, rn, imm3, true);
185 return new SubImmCc(machInst, rd, rn, imm3, true);
186 }
187 case 0x4:
186 }
187 case 0x4:
188 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, true);
188 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
189 case 0x5:
190 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
191 case 0x6:
189 case 0x5:
190 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
191 case 0x6:
192 return new AddImm(machInst, rd8, rd8, imm8, true);
192 return new AddImmCc(machInst, rd8, rd8, imm8, true);
193 case 0x7:
193 case 0x7:
194 return new SubImm(machInst, rd8, rd8, imm8, true);
194 return new SubImmCc(machInst, rd8, rd8, imm8, true);
195 }
196 }
197 '''
198}};
199
200def format Thumb16DataProcessing() {{
201 decode_block = '''
202 {
203 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
204 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
205 switch (bits(machInst, 9, 6)) {
206 case 0x0:
195 }
196 }
197 '''
198}};
199
200def format Thumb16DataProcessing() {{
201 decode_block = '''
202 {
203 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
204 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
205 switch (bits(machInst, 9, 6)) {
206 case 0x0:
207 return new AndReg(machInst, rdn, rdn, rm, 0, LSL);
207 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL);
208 case 0x1:
208 case 0x1:
209 return new EorReg(machInst, rdn, rdn, rm, 0, LSL);
209 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL);
210 case 0x2: //lsl
210 case 0x2: //lsl
211 return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
211 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
212 case 0x3: //lsr
212 case 0x3: //lsr
213 return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
213 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
214 case 0x4: //asr
214 case 0x4: //asr
215 return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
215 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
216 case 0x5:
216 case 0x5:
217 return new AdcReg(machInst, rdn, rdn, rm, 0, LSL);
217 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL);
218 case 0x6:
218 case 0x6:
219 return new SbcReg(machInst, rdn, rdn, rm, 0, LSL);
219 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL);
220 case 0x7: // ror
220 case 0x7: // ror
221 return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
221 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
222 case 0x8:
222 case 0x8:
223 return new TstReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
223 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
224 case 0x9:
224 case 0x9:
225 return new RsbImm(machInst, rdn, rm, 0, true);
225 return new RsbImmCc(machInst, rdn, rm, 0, true);
226 case 0xa:
226 case 0xa:
227 return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
227 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
228 case 0xb:
228 case 0xb:
229 return new CmnReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
229 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
230 case 0xc:
230 case 0xc:
231 return new OrrReg(machInst, rdn, rdn, rm, 0, LSL);
231 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL);
232 case 0xd:
232 case 0xd:
233 return new Mul(machInst, rdn, rm, rdn);
233 return new MulCc(machInst, rdn, rm, rdn);
234 case 0xe:
234 case 0xe:
235 return new BicReg(machInst, rdn, rdn, rm, 0, LSL);
235 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
236 case 0xf:
236 case 0xf:
237 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
237 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
238 }
239 }
240 '''
241}};
242
243def format Thumb16SpecDataAndBx() {{
244 decode_block = '''
245 {
246 const IntRegIndex rdn =
247 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
248 (bits(machInst, 7) << 3));
249 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
250 switch (bits(machInst, 9, 8)) {
251 case 0x0:
252 return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
253 case 0x1:
238 }
239 }
240 '''
241}};
242
243def format Thumb16SpecDataAndBx() {{
244 decode_block = '''
245 {
246 const IntRegIndex rdn =
247 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
248 (bits(machInst, 7) << 3));
249 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
250 switch (bits(machInst, 9, 8)) {
251 case 0x0:
252 return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
253 case 0x1:
254 return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
254 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
255 case 0x2:
256 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
257 case 0x3:
258 if (bits(machInst, 7) == 0) {
259 return new BxReg(machInst,
260 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
261 COND_UC);
262 } else {

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387}};
388
389def format Thumb32DataProcModImm() {{
390
391 def decInst(mnem, dest="rd", op1="rn"):
392 return '''
393 if (s) {
394 return new %(mnem)sImmCc(machInst, %(dest)s,
255 case 0x2:
256 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
257 case 0x3:
258 if (bits(machInst, 7) == 0) {
259 return new BxReg(machInst,
260 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
261 COND_UC);
262 } else {

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387}};
388
389def format Thumb32DataProcModImm() {{
390
391 def decInst(mnem, dest="rd", op1="rn"):
392 return '''
393 if (s) {
394 return new %(mnem)sImmCc(machInst, %(dest)s,
395 %(op1)s, imm, true);
395 %(op1)s, imm, rotC);
396 } else {
397 return new %(mnem)sImm(machInst, %(dest)s,
396 } else {
397 return new %(mnem)sImm(machInst, %(dest)s,
398 %(op1)s, imm, true);
398 %(op1)s, imm, rotC);
399 }
400 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
401
402 decode_block = '''
403 {
404 const uint32_t op = bits(machInst, 24, 21);
405 const bool s = (bits(machInst, 20) == 1);
406 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
407 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
408 const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
409 bits(machInst, 14, 12);
399 }
400 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
401
402 decode_block = '''
403 {
404 const uint32_t op = bits(machInst, 24, 21);
405 const bool s = (bits(machInst, 20) == 1);
406 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
407 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
408 const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
409 bits(machInst, 14, 12);
410 const bool rotC = ctrlImm > 3;
410 const uint32_t dataImm = bits(machInst, 7, 0);
411 const uint32_t imm = modified_imm(ctrlImm, dataImm);
412 switch (op) {
413 case 0x0:
414 if (rd == INTREG_PC) {
415 %(tst)s
416 } else {
417 %(and)s

--- 224 unchanged lines hidden --- 		411 const uint32_t dataImm = bits(machInst, 7, 0);
412 const uint32_t imm = modified_imm(ctrlImm, dataImm);
413 switch (op) {
414 case 0x0:
415 if (rd == INTREG_PC) {
416 %(tst)s
417 } else {
418 %(and)s

--- 224 unchanged lines hidden ---