data.isa (7146:f68d5f1f748c) data.isa (7154:1fa6d1db1f32)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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251 switch (bits(machInst, 9, 8)) {
252 case 0x0:
253 return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
254 case 0x1:
255 return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
256 case 0x2:
257 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
258 case 0x3:
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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251 switch (bits(machInst, 9, 8)) {
252 case 0x0:
253 return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
254 case 0x1:
255 return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
256 case 0x2:
257 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
258 case 0x3:
259 if (bits(machInst, 7) == 0)
260 return new WarnUnimplemented("bx", machInst);
261 else
262 // The register version.
263 return new WarnUnimplemented("blx", machInst);
259 if (bits(machInst, 7) == 0) {
260 return new BxReg(machInst,
261 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
262 COND_UC);
263 } else {
264 return new BlxReg(machInst,
265 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
266 COND_UC);
267 }
264 }
265 }
266 '''
267}};
268
269def format Thumb16Adr() {{
270 decode_block = '''
271 {

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294 if (bits(machInst, 7)) {
295 return new SubImm(machInst, INTREG_SP, INTREG_SP,
296 bits(machInst, 6, 0) << 2, true);
297 } else {
298 return new AddImm(machInst, INTREG_SP, INTREG_SP,
299 bits(machInst, 6, 0) << 2, true);
300 }
301 case 0x1:
268 }
269 }
270 '''
271}};
272
273def format Thumb16Adr() {{
274 decode_block = '''
275 {

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298 if (bits(machInst, 7)) {
299 return new SubImm(machInst, INTREG_SP, INTREG_SP,
300 bits(machInst, 6, 0) << 2, true);
301 } else {
302 return new AddImm(machInst, INTREG_SP, INTREG_SP,
303 bits(machInst, 6, 0) << 2, true);
304 }
305 case 0x1:
302 return new WarnUnimplemented("cbz", machInst);
306 return new Cbz(machInst,
307 (bits(machInst, 9) << 6) |
308 (bits(machInst, 7, 3) << 1),
309 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
303 case 0x2:
304 switch (bits(machInst, 7, 6)) {
305 case 0x0:
306 return new WarnUnimplemented("sxth", machInst);
307 case 0x1:
308 return new WarnUnimplemented("sxtb", machInst);
309 case 0x2:
310 return new WarnUnimplemented("uxth", machInst);
311 case 0x3:
312 return new WarnUnimplemented("uxtb", machInst);
313 }
314 case 0x3:
310 case 0x2:
311 switch (bits(machInst, 7, 6)) {
312 case 0x0:
313 return new WarnUnimplemented("sxth", machInst);
314 case 0x1:
315 return new WarnUnimplemented("sxtb", machInst);
316 case 0x2:
317 return new WarnUnimplemented("uxth", machInst);
318 case 0x3:
319 return new WarnUnimplemented("uxtb", machInst);
320 }
321 case 0x3:
315 return new WarnUnimplemented("cbnz", machInst);
322 return new Cbz(machInst,
323 (bits(machInst, 9) << 6) |
324 (bits(machInst, 7, 3) << 1),
325 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
316 case 0x4:
317 case 0x5:
318 return new WarnUnimplemented("push", machInst);
319 case 0x6:
320 {
321 const uint32_t opBits = bits(machInst, 7, 5);
322 if (opBits == 2) {
323 return new WarnUnimplemented("setend", machInst);
324 } else if (opBits == 3) {
325 return new WarnUnimplemented("cps", machInst);
326 }
327 }
328 case 0x9:
326 case 0x4:
327 case 0x5:
328 return new WarnUnimplemented("push", machInst);
329 case 0x6:
330 {
331 const uint32_t opBits = bits(machInst, 7, 5);
332 if (opBits == 2) {
333 return new WarnUnimplemented("setend", machInst);
334 } else if (opBits == 3) {
335 return new WarnUnimplemented("cps", machInst);
336 }
337 }
338 case 0x9:
329 return new WarnUnimplemented("cbz", machInst);
339 return new Cbnz(machInst,
340 (bits(machInst, 9) << 6) |
341 (bits(machInst, 7, 3) << 1),
342 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
330 case 0xa:
331 switch (bits(machInst, 7, 5)) {
332 case 0x0:
333 return new WarnUnimplemented("rev", machInst);
334 case 0x1:
335 return new WarnUnimplemented("rev16", machInst);
336 case 0x3:
337 return new WarnUnimplemented("revsh", machInst);
338 default:
339 break;
340 }
341 break;
342 case 0xb:
343 case 0xa:
344 switch (bits(machInst, 7, 5)) {
345 case 0x0:
346 return new WarnUnimplemented("rev", machInst);
347 case 0x1:
348 return new WarnUnimplemented("rev16", machInst);
349 case 0x3:
350 return new WarnUnimplemented("revsh", machInst);
351 default:
352 break;
353 }
354 break;
355 case 0xb:
343 return new WarnUnimplemented("cbnz", machInst);
356 return new Cbnz(machInst,
357 (bits(machInst, 9) << 6) |
358 (bits(machInst, 7, 3) << 1),
359 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
344 case 0xc:
345 case 0xd:
346 return new WarnUnimplemented("pop", machInst);
347 case 0xe:
348 return new WarnUnimplemented("bkpt", machInst);
349 case 0xf:
350 if (bits(machInst, 3, 0) != 0)
351 return new WarnUnimplemented("it", machInst);

--- 207 unchanged lines hidden --- 		360 case 0xc:
361 case 0xd:
362 return new WarnUnimplemented("pop", machInst);
363 case 0xe:
364 return new WarnUnimplemented("bkpt", machInst);
365 case 0xf:
366 if (bits(machInst, 3, 0) != 0)
367 return new WarnUnimplemented("it", machInst);

--- 207 unchanged lines hidden ---