data.isa (7141:423e3dce3e27) data.isa (7146:f68d5f1f748c)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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35//
36// Authors: Gabe Black
37
38def format ArmDataProcReg() {{
39 instDecode = '''
40 case %(opcode)#x:
41 if (immShift) {
42 if (setCc) {
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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35//
36// Authors: Gabe Black
37
38def format ArmDataProcReg() {{
39 instDecode = '''
40 case %(opcode)#x:
41 if (immShift) {
42 if (setCc) {
43 return new %(className)sDRegCc(machInst, %(dest)s, %(op1)s,
43 return new %(className)sRegCc(machInst, %(dest)s, %(op1)s,
44 rm, imm5, type);
45 } else {
44 rm, imm5, type);
45 } else {
46 return new %(className)sDReg(machInst, %(dest)s, %(op1)s,
46 return new %(className)sReg(machInst, %(dest)s, %(op1)s,
47 rm, imm5, type);
48 }
49 } else {
50 if (setCc) {
47 rm, imm5, type);
48 }
49 } else {
50 if (setCc) {
51 return new %(className)sDRegRegCc(machInst, %(dest)s,
51 return new %(className)sRegRegCc(machInst, %(dest)s,
52 %(op1)s, rm, rs, type);
53 } else {
52 %(op1)s, rm, rs, type);
53 } else {
54 return new %(className)sDRegReg(machInst, %(dest)s,
54 return new %(className)sRegReg(machInst, %(dest)s,
55 %(op1)s, rm, rs, type);
56 }
57 }
58 break;
59 '''
60
61 def instCode(opcode, mnem, dest="rd", op1="rn"):
62 global instDecode

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100 }
101 '''
102}};
103
104def format ArmDataProcImm() {{
105 instDecode = '''
106 case %(opcode)#x:
107 if (setCc) {
55 %(op1)s, rm, rs, type);
56 }
57 }
58 break;
59 '''
60
61 def instCode(opcode, mnem, dest="rd", op1="rn"):
62 global instDecode

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100 }
101 '''
102}};
103
104def format ArmDataProcImm() {{
105 instDecode = '''
106 case %(opcode)#x:
107 if (setCc) {
108 return new %(className)sDImmCc(machInst, %(dest)s, %(op1)s,
108 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
109 imm, rotC);
110 } else {
109 imm, rotC);
110 } else {
111 return new %(className)sDImm(machInst, %(dest)s, %(op1)s,
111 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
112 imm, rotC);
113 }
114 break;
115 '''
116
117 def instCode(opcode, mnem, dest="rd", op1="rn"):
118 global instDecode
119 return instDecode % { "className": mnem.capitalize(),

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163 const uint32_t imm3 = bits(machInst, 8, 6);
164 const uint32_t imm8 = bits(machInst, 7, 0);
165 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
166 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
167 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
168 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
169 switch (bits(machInst, 13, 11)) {
170 case 0x0: // lsl
112 imm, rotC);
113 }
114 break;
115 '''
116
117 def instCode(opcode, mnem, dest="rd", op1="rn"):
118 global instDecode
119 return instDecode % { "className": mnem.capitalize(),

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163 const uint32_t imm3 = bits(machInst, 8, 6);
164 const uint32_t imm8 = bits(machInst, 7, 0);
165 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
166 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
167 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
168 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
169 switch (bits(machInst, 13, 11)) {
170 case 0x0: // lsl
171 return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
171 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
172 case 0x1: // lsr
172 case 0x1: // lsr
173 return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
173 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
174 case 0x2: // asr
174 case 0x2: // asr
175 return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
175 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
176 case 0x3:
177 switch (bits(machInst, 10, 9)) {
178 case 0x0:
176 case 0x3:
177 switch (bits(machInst, 10, 9)) {
178 case 0x0:
179 return new AddDReg(machInst, rd, rn, rm, 0, LSL);
179 return new AddReg(machInst, rd, rn, rm, 0, LSL);
180 case 0x1:
180 case 0x1:
181 return new SubDReg(machInst, rd, rn, rm, 0, LSL);
181 return new SubReg(machInst, rd, rn, rm, 0, LSL);
182 case 0x2:
182 case 0x2:
183 return new AddDImm(machInst, rd, rn, imm3, true);
183 return new AddImm(machInst, rd, rn, imm3, true);
184 case 0x3:
184 case 0x3:
185 return new SubDImm(machInst, rd, rn, imm3, true);
185 return new SubImm(machInst, rd, rn, imm3, true);
186 }
187 case 0x4:
186 }
187 case 0x4:
188 return new MovDImm(machInst, rd8, INTREG_ZERO, imm8, true);
188 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, true);
189 case 0x5:
189 case 0x5:
190 return new CmpDImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
190 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
191 case 0x6:
191 case 0x6:
192 return new AddDImm(machInst, rd8, rd8, imm8, true);
192 return new AddImm(machInst, rd8, rd8, imm8, true);
193 case 0x7:
193 case 0x7:
194 return new SubDImm(machInst, rd8, rd8, imm8, true);
194 return new SubImm(machInst, rd8, rd8, imm8, true);
195 }
196 }
197 '''
198}};
199
200def format Thumb16DataProcessing() {{
201 decode_block = '''
202 {
203 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
204 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
205 switch (bits(machInst, 9, 6)) {
206 case 0x0:
195 }
196 }
197 '''
198}};
199
200def format Thumb16DataProcessing() {{
201 decode_block = '''
202 {
203 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
204 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
205 switch (bits(machInst, 9, 6)) {
206 case 0x0:
207 return new AndDReg(machInst, rdn, rdn, rm, 0, LSL);
207 return new AndReg(machInst, rdn, rdn, rm, 0, LSL);
208 case 0x1:
208 case 0x1:
209 return new EorDReg(machInst, rdn, rdn, rm, 0, LSL);
209 return new EorReg(machInst, rdn, rdn, rm, 0, LSL);
210 case 0x2: //lsl
210 case 0x2: //lsl
211 return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
211 return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
212 case 0x3: //lsr
212 case 0x3: //lsr
213 return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
213 return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
214 case 0x4: //asr
214 case 0x4: //asr
215 return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
215 return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
216 case 0x5:
216 case 0x5:
217 return new AdcDReg(machInst, rdn, rdn, rm, 0, LSL);
217 return new AdcReg(machInst, rdn, rdn, rm, 0, LSL);
218 case 0x6:
218 case 0x6:
219 return new SbcDReg(machInst, rdn, rdn, rm, 0, LSL);
219 return new SbcReg(machInst, rdn, rdn, rm, 0, LSL);
220 case 0x7: // ror
220 case 0x7: // ror
221 return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
221 return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
222 case 0x8:
222 case 0x8:
223 return new TstDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
223 return new TstReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
224 case 0x9:
224 case 0x9:
225 return new RsbDImm(machInst, rdn, rm, 0, true);
225 return new RsbImm(machInst, rdn, rm, 0, true);
226 case 0xa:
226 case 0xa:
227 return new CmpDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
227 return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
228 case 0xb:
228 case 0xb:
229 return new CmnDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
229 return new CmnReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
230 case 0xc:
230 case 0xc:
231 return new OrrDReg(machInst, rdn, rdn, rm, 0, LSL);
231 return new OrrReg(machInst, rdn, rdn, rm, 0, LSL);
232 case 0xd:
233 //XXX Implement me!
234 return new WarnUnimplemented("mul", machInst);
235 case 0xe:
232 case 0xd:
233 //XXX Implement me!
234 return new WarnUnimplemented("mul", machInst);
235 case 0xe:
236 return new BicDReg(machInst, rdn, rdn, rm, 0, LSL);
236 return new BicReg(machInst, rdn, rdn, rm, 0, LSL);
237 case 0xf:
237 case 0xf:
238 return new MvnDReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
238 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
239 }
240 }
241 '''
242}};
243
244def format Thumb16SpecDataAndBx() {{
245 decode_block = '''
246 {
247 const IntRegIndex rdn =
248 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
249 (bits(machInst, 7) << 3));
250 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
251 switch (bits(machInst, 9, 8)) {
252 case 0x0:
239 }
240 }
241 '''
242}};
243
244def format Thumb16SpecDataAndBx() {{
245 decode_block = '''
246 {
247 const IntRegIndex rdn =
248 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
249 (bits(machInst, 7) << 3));
250 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
251 switch (bits(machInst, 9, 8)) {
252 case 0x0:
253 return new AddDReg(machInst, rdn, rdn, rm, 0, LSL);
253 return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
254 case 0x1:
254 case 0x1:
255 return new CmpDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
255 return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
256 case 0x2:
256 case 0x2:
257 return new MovDReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
257 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
258 case 0x3:
259 if (bits(machInst, 7) == 0)
260 return new WarnUnimplemented("bx", machInst);
261 else
262 // The register version.
263 return new WarnUnimplemented("blx", machInst);
264 }
265 }
266 '''
267}};
268
269def format Thumb16Adr() {{
270 decode_block = '''
271 {
272 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
273 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
258 case 0x3:
259 if (bits(machInst, 7) == 0)
260 return new WarnUnimplemented("bx", machInst);
261 else
262 // The register version.
263 return new WarnUnimplemented("blx", machInst);
264 }
265 }
266 '''
267}};
268
269def format Thumb16Adr() {{
270 decode_block = '''
271 {
272 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
273 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
274 return new AddDImm(machInst, rd, INTREG_PC, imm8, true);
274 return new AddImm(machInst, rd, INTREG_PC, imm8, true);
275 }
276 '''
277}};
278
279def format Thumb16AddSp() {{
280 decode_block = '''
281 {
282 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
283 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
275 }
276 '''
277}};
278
279def format Thumb16AddSp() {{
280 decode_block = '''
281 {
282 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
283 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
284 return new AddDImm(machInst, rd, INTREG_SP, imm8, true);
284 return new AddImm(machInst, rd, INTREG_SP, imm8, true);
285 }
286 '''
287}};
288
289def format Thumb16Misc() {{
290 decode_block = '''
291 {
292 switch (bits(machInst, 11, 8)) {
293 case 0x0:
294 if (bits(machInst, 7)) {
285 }
286 '''
287}};
288
289def format Thumb16Misc() {{
290 decode_block = '''
291 {
292 switch (bits(machInst, 11, 8)) {
293 case 0x0:
294 if (bits(machInst, 7)) {
295 return new SubDImm(machInst, INTREG_SP, INTREG_SP,
295 return new SubImm(machInst, INTREG_SP, INTREG_SP,
296 bits(machInst, 6, 0) << 2, true);
297 } else {
296 bits(machInst, 6, 0) << 2, true);
297 } else {
298 return new AddDImm(machInst, INTREG_SP, INTREG_SP,
298 return new AddImm(machInst, INTREG_SP, INTREG_SP,
299 bits(machInst, 6, 0) << 2, true);
300 }
301 case 0x1:
302 return new WarnUnimplemented("cbz", machInst);
303 case 0x2:
304 switch (bits(machInst, 7, 6)) {
305 case 0x0:
306 return new WarnUnimplemented("sxth", machInst);

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371 '''
372}};
373
374def format Thumb32DataProcModImm() {{
375
376 def decInst(mnem, dest="rd", op1="rn"):
377 return '''
378 if (s) {
299 bits(machInst, 6, 0) << 2, true);
300 }
301 case 0x1:
302 return new WarnUnimplemented("cbz", machInst);
303 case 0x2:
304 switch (bits(machInst, 7, 6)) {
305 case 0x0:
306 return new WarnUnimplemented("sxth", machInst);

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371 '''
372}};
373
374def format Thumb32DataProcModImm() {{
375
376 def decInst(mnem, dest="rd", op1="rn"):
377 return '''
378 if (s) {
379 return new %(mnem)sDImmCc(machInst, %(dest)s,
379 return new %(mnem)sImmCc(machInst, %(dest)s,
380 %(op1)s, imm, true);
381 } else {
380 %(op1)s, imm, true);
381 } else {
382 return new %(mnem)sDImm(machInst, %(dest)s,
382 return new %(mnem)sImm(machInst, %(dest)s,
383 %(op1)s, imm, true);
384 }
385 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
386
387 decode_block = '''
388 {
389 const uint32_t op = bits(machInst, 24, 21);
390 const bool s = (bits(machInst, 20) == 1);

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463 }
464}};
465
466def format Thumb32DataProcShiftReg() {{
467
468 def decInst(mnem, dest="rd", op1="rn"):
469 return '''
470 if (s) {
383 %(op1)s, imm, true);
384 }
385 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
386
387 decode_block = '''
388 {
389 const uint32_t op = bits(machInst, 24, 21);
390 const bool s = (bits(machInst, 20) == 1);

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463 }
464}};
465
466def format Thumb32DataProcShiftReg() {{
467
468 def decInst(mnem, dest="rd", op1="rn"):
469 return '''
470 if (s) {
471 return new %(mnem)sDRegCc(machInst, %(dest)s,
471 return new %(mnem)sRegCc(machInst, %(dest)s,
472 %(op1)s, rm, amt, type);
473 } else {
472 %(op1)s, rm, amt, type);
473 } else {
474 return new %(mnem)sDReg(machInst, %(dest)s,
474 return new %(mnem)sReg(machInst, %(dest)s,
475 %(op1)s, rm, amt, type);
476 }
477 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
478
479 decode_block = '''
480 {
481 const uint32_t op = bits(machInst, 24, 21);
482 const bool s = (bits(machInst, 20) == 1);

--- 76 unchanged lines hidden --- 		475 %(op1)s, rm, amt, type);
476 }
477 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
478
479 decode_block = '''
480 {
481 const uint32_t op = bits(machInst, 24, 21);
482 const bool s = (bits(machInst, 20) == 1);

--- 76 unchanged lines hidden ---