data.isa (12542:03cb745f9982) data.isa (12595:b5a51007feac)
1// Copyright (c) 2010,2017-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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71 }
72 return new Unknown(machInst);
73 }
74 '''
75}};
76
77def format ArmDataProcReg() {{
78 pclr = '''
1// Copyright (c) 2010,2017-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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71 }
72 return new Unknown(machInst);
73 }
74 '''
75}};
76
77def format ArmDataProcReg() {{
78 pclr = '''
79 return new %(className)ssRegPclr(machInst, %(dest)s,
80 %(op1)s, rm, imm5,
81 type);
79 if (%(dest)s == INTREG_PC) {
80 return new %(className)ssRegPclr(machInst, %(dest)s,
81 %(op1)s, rm, imm5,
82 type);
83 } else
82 '''
83 instDecode = '''
84 case %(opcode)#x:
85 if (immShift) {
86 if (setCc) {
84 '''
85 instDecode = '''
86 case %(opcode)#x:
87 if (immShift) {
88 if (setCc) {
87 if (%(dest)s == INTREG_PC) {
88 %(pclr)s
89 } else {
89 %(pclr)s {
90 return new %(className)sRegCc(machInst, %(dest)s,
91 %(op1)s, rm, imm5, type);
92 }
93 } else {
94 return new %(className)sReg(machInst, %(dest)s, %(op1)s,
95 rm, imm5, type);
96 }
97 } else {

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447 }
448 return new Unknown(machInst);
449 }
450 '''
451}};
452
453def format ArmDataProcImm() {{
454 pclr = '''
90 return new %(className)sRegCc(machInst, %(dest)s,
91 %(op1)s, rm, imm5, type);
92 }
93 } else {
94 return new %(className)sReg(machInst, %(dest)s, %(op1)s,
95 rm, imm5, type);
96 }
97 } else {

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447 }
448 return new Unknown(machInst);
449 }
450 '''
451}};
452
453def format ArmDataProcImm() {{
454 pclr = '''
455 return new %(className)ssImmPclr(machInst, %(dest)s,
456 %(op1)s, imm, false);
455 if (%(dest)s == INTREG_PC) {
456 return new %(className)ssImmPclr(machInst, %(dest)s,
457 %(op1)s, imm, false);
458 } else
457 '''
458 adr = '''
459 '''
460 adr = '''
459 return new AdrImm(machInst, %(dest)s, %(add)s,
460 imm, false);
461 if (%(op1)s == INTREG_PC) {
462 return new AdrImm(machInst, %(dest)s, %(add)s,
463 imm, false);
464 } else
461 '''
462 instDecode = '''
463 case %(opcode)#x:
464 if (setCc) {
465 '''
466 instDecode = '''
467 case %(opcode)#x:
468 if (setCc) {
465 if (%(pclrInst)s && %(dest)s == INTREG_PC) {
466 %(pclr)s
467 } else {
469 %(pclr)s {
468 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
469 imm, rotC);
470 }
471 } else {
470 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
471 imm, rotC);
472 }
473 } else {
472 if (%(adrInst)s && %(op1)s == INTREG_PC) {
473 %(adr)s
474 } else {
474 %(adr)s {
475 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
476 imm, rotC);
477 }
478 }
479 break;
480 '''
481
482 def instCode(opcode, mnem, useDest = True, useOp1 = True):

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488 if useOp1:
489 op1 = "rn"
490 else:
491 op1 = "INTREG_ZERO"
492 substDict = { "className": mnem.capitalize(),
493 "opcode": opcode,
494 "dest": dest,
495 "op1": op1,
475 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
476 imm, rotC);
477 }
478 }
479 break;
480 '''
481
482 def instCode(opcode, mnem, useDest = True, useOp1 = True):

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488 if useOp1:
489 op1 = "rn"
490 else:
491 op1 = "INTREG_ZERO"
492 substDict = { "className": mnem.capitalize(),
493 "opcode": opcode,
494 "dest": dest,
495 "op1": op1,
496 "adr": "",
497 "adrInst": "false" }
496 "adr": "" }
498 if useDest:
497 if useDest:
499 substDict["pclrInst"] = "true"
500 substDict["pclr"] = pclr % substDict
501 else:
498 substDict["pclr"] = pclr % substDict
499 else:
502 substDict["pclrInst"] = "false"
503 substDict["pclr"] = ""
504 return instDecode % substDict
505
506 def adrCode(opcode, mnem, add="1"):
507 global instDecode, pclr, adr
508 substDict = { "className": mnem.capitalize(),
509 "opcode": opcode,
510 "dest": "rd",
511 "op1": "rn",
500 substDict["pclr"] = ""
501 return instDecode % substDict
502
503 def adrCode(opcode, mnem, add="1"):
504 global instDecode, pclr, adr
505 substDict = { "className": mnem.capitalize(),
506 "opcode": opcode,
507 "dest": "rd",
508 "op1": "rn",
512 "add": add,
513 "pclrInst": "true",
514 "adrInst": "true" }
509 "add": add }
515 substDict["pclr"] = pclr % substDict
516 substDict["adr"] = adr % substDict
517 return instDecode % substDict
518
519 decode_block = '''
520 {
521 const bool setCc = (bits(machInst, 20) == 1);
522 const uint32_t unrotated = bits(machInst, 7, 0);

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606 return new MovRegRegCc(machInst, rd,
607 INTREG_ZERO, rn, rm, ASR);
608 case 0x6:
609 return new MovRegReg(machInst, rd,
610 INTREG_ZERO, rn, rm, ROR);
611 case 0x7:
612 return new MovRegRegCc(machInst, rd,
613 INTREG_ZERO, rn, rm, ROR);
510 substDict["pclr"] = pclr % substDict
511 substDict["adr"] = adr % substDict
512 return instDecode % substDict
513
514 decode_block = '''
515 {
516 const bool setCc = (bits(machInst, 20) == 1);
517 const uint32_t unrotated = bits(machInst, 7, 0);

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601 return new MovRegRegCc(machInst, rd,
602 INTREG_ZERO, rn, rm, ASR);
603 case 0x6:
604 return new MovRegReg(machInst, rd,
605 INTREG_ZERO, rn, rm, ROR);
606 case 0x7:
607 return new MovRegRegCc(machInst, rd,
608 INTREG_ZERO, rn, rm, ROR);
609 default:
610 M5_UNREACHABLE;
614 }
615 } else if (bits(op2, 3) == 0) {
616 return new Unknown(machInst);
617 } else {
618 const IntRegIndex rd =
619 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
620 const IntRegIndex rm =
621 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);

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911 return new AddImmCc(machInst, rd, rn, imm3, true);
912 }
913 case 0x3:
914 if (machInst.itstateMask) {
915 return new SubImm(machInst, rd, rn, imm3, true);
916 } else {
917 return new SubImmCc(machInst, rd, rn, imm3, true);
918 }
611 }
612 } else if (bits(op2, 3) == 0) {
613 return new Unknown(machInst);
614 } else {
615 const IntRegIndex rd =
616 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
617 const IntRegIndex rm =
618 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);

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908 return new AddImmCc(machInst, rd, rn, imm3, true);
909 }
910 case 0x3:
911 if (machInst.itstateMask) {
912 return new SubImm(machInst, rd, rn, imm3, true);
913 } else {
914 return new SubImmCc(machInst, rd, rn, imm3, true);
915 }
916 default:
917 M5_UNREACHABLE;
919 }
920 case 0x4:
921 if (machInst.itstateMask) {
922 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false);
923 } else {
924 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
925 }
926 case 0x5:

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932 return new AddImmCc(machInst, rd8, rd8, imm8, true);
933 }
934 case 0x7:
935 if (machInst.itstateMask) {
936 return new SubImm(machInst, rd8, rd8, imm8, true);
937 } else {
938 return new SubImmCc(machInst, rd8, rd8, imm8, true);
939 }
918 }
919 case 0x4:
920 if (machInst.itstateMask) {
921 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false);
922 } else {
923 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
924 }
925 case 0x5:

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931 return new AddImmCc(machInst, rd8, rd8, imm8, true);
932 }
933 case 0x7:
934 if (machInst.itstateMask) {
935 return new SubImm(machInst, rd8, rd8, imm8, true);
936 } else {
937 return new SubImmCc(machInst, rd8, rd8, imm8, true);
938 }
939 default:
940 M5_UNREACHABLE;
940 }
941 }
942 '''
943}};
944
945def format Thumb16DataProcessing() {{
946 decode_block = '''
947 {

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1035 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
1036 }
1037 case 0xf:
1038 if (machInst.itstateMask) {
1039 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1040 } else {
1041 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1042 }
941 }
942 }
943 '''
944}};
945
946def format Thumb16DataProcessing() {{
947 decode_block = '''
948 {

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1036 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
1037 }
1038 case 0xf:
1039 if (machInst.itstateMask) {
1040 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1041 } else {
1042 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1043 }
1044 default:
1045 M5_UNREACHABLE;
1043 }
1044 }
1045 '''
1046}};
1047
1048def format Thumb16SpecDataAndBx() {{
1049 decode_block = '''
1050 {

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1064 return new BxReg(machInst,
1065 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
1066 COND_UC);
1067 } else {
1068 return new BlxReg(machInst,
1069 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
1070 COND_UC);
1071 }
1046 }
1047 }
1048 '''
1049}};
1050
1051def format Thumb16SpecDataAndBx() {{
1052 decode_block = '''
1053 {

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1067 return new BxReg(machInst,
1068 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
1069 COND_UC);
1070 } else {
1071 return new BlxReg(machInst,
1072 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
1073 COND_UC);
1074 }
1075 default:
1076 M5_UNREACHABLE;
1072 }
1073 }
1074 '''
1075}};
1076
1077def format Thumb16Adr() {{
1078 decode_block = '''
1079 {

--- 84 unchanged lines hidden (view full) ---

1164 case 0x0:
1165 return new Sxth(machInst, rd, 0, rm);
1166 case 0x1:
1167 return new Sxtb(machInst, rd, 0, rm);
1168 case 0x2:
1169 return new Uxth(machInst, rd, 0, rm);
1170 case 0x3:
1171 return new Uxtb(machInst, rd, 0, rm);
1077 }
1078 }
1079 '''
1080}};
1081
1082def format Thumb16Adr() {{
1083 decode_block = '''
1084 {

--- 84 unchanged lines hidden (view full) ---

1169 case 0x0:
1170 return new Sxth(machInst, rd, 0, rm);
1171 case 0x1:
1172 return new Sxtb(machInst, rd, 0, rm);
1173 case 0x2:
1174 return new Uxth(machInst, rd, 0, rm);
1175 case 0x3:
1176 return new Uxtb(machInst, rd, 0, rm);
1177 default:
1178 M5_UNREACHABLE;
1172 }
1173 }
1174 case 0x1:
1175 case 0x3:
1176 return new Cbz(machInst,
1177 (bits(machInst, 9) << 6) |
1178 (bits(machInst, 7, 3) << 1),
1179 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));

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1191 if (opBits == 2) {
1192 return new Setend(machInst, bits(machInst, 3));
1193 } else if (opBits == 3) {
1194 const bool enable = (bits(machInst, 4) == 0);
1195 const uint32_t mods = (bits(machInst, 2, 0) << 5) |
1196 ((enable ? 1 : 0) << 9);
1197 return new Cps(machInst, mods);
1198 }
1179 }
1180 }
1181 case 0x1:
1182 case 0x3:
1183 return new Cbz(machInst,
1184 (bits(machInst, 9) << 6) |
1185 (bits(machInst, 7, 3) << 1),
1186 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));

--- 11 unchanged lines hidden (view full) ---

1198 if (opBits == 2) {
1199 return new Setend(machInst, bits(machInst, 3));
1200 } else if (opBits == 3) {
1201 const bool enable = (bits(machInst, 4) == 0);
1202 const uint32_t mods = (bits(machInst, 2, 0) << 5) |
1203 ((enable ? 1 : 0) << 9);
1204 return new Cps(machInst, mods);
1205 }
1206 return new Unknown(machInst);
1199 }
1200 case 0xa:
1201 {
1202 const uint8_t op1 = bits(machInst, 7, 6);
1203 if (op1 == 0x2) {
1204 return new Hlt(machInst, bits(machInst, 5, 0));
1205 } else {
1206 IntRegIndex rd =

--- 195 unchanged lines hidden (view full) ---

1402 (bits(machInst, 19, 16) << 12);
1403 return new MovtImm(machInst, rd, rd, imm, true);
1404 }
1405 case 0x12:
1406 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1407 const uint32_t satImm = bits(machInst, 4, 0);
1408 return new Ssat16(machInst, rd, satImm + 1, rn);
1409 }
1207 }
1208 case 0xa:
1209 {
1210 const uint8_t op1 = bits(machInst, 7, 6);
1211 if (op1 == 0x2) {
1212 return new Hlt(machInst, bits(machInst, 5, 0));
1213 } else {
1214 IntRegIndex rd =

--- 195 unchanged lines hidden (view full) ---

1410 (bits(machInst, 19, 16) << 12);
1411 return new MovtImm(machInst, rd, rd, imm, true);
1412 }
1413 case 0x12:
1414 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1415 const uint32_t satImm = bits(machInst, 4, 0);
1416 return new Ssat16(machInst, rd, satImm + 1, rn);
1417 }
1410 // Fall through on purpose...
1418 M5_FALLTHROUGH;
1411 case 0x10:
1412 {
1413 const uint32_t satImm = bits(machInst, 4, 0);
1414 const uint32_t imm = bits(machInst, 7, 6) |
1415 (bits(machInst, 14, 12) << 2);
1416 const ArmShiftType type =
1417 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1418 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);

--- 16 unchanged lines hidden (view full) ---

1435 return new Bfi(machInst, rd, rn, lsb, msb);
1436 }
1437 }
1438 case 0x1a:
1439 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1440 const uint32_t satImm = bits(machInst, 4, 0);
1441 return new Usat16(machInst, rd, satImm, rn);
1442 }
1419 case 0x10:
1420 {
1421 const uint32_t satImm = bits(machInst, 4, 0);
1422 const uint32_t imm = bits(machInst, 7, 6) |
1423 (bits(machInst, 14, 12) << 2);
1424 const ArmShiftType type =
1425 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1426 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);

--- 16 unchanged lines hidden (view full) ---

1443 return new Bfi(machInst, rd, rn, lsb, msb);
1444 }
1445 }
1446 case 0x1a:
1447 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1448 const uint32_t satImm = bits(machInst, 4, 0);
1449 return new Usat16(machInst, rd, satImm, rn);
1450 }
1443 // Fall through on purpose...
1451 M5_FALLTHROUGH;
1444 case 0x18:
1445 {
1446 const uint32_t satImm = bits(machInst, 4, 0);
1447 const uint32_t imm = bits(machInst, 7, 6) |
1448 (bits(machInst, 14, 12) << 2);
1449 const ArmShiftType type =
1450 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1451 return new Usat(machInst, rd, satImm, rn, imm, type);

--- 112 unchanged lines hidden --- 		1452 case 0x18:
1453 {
1454 const uint32_t satImm = bits(machInst, 4, 0);
1455 const uint32_t imm = bits(machInst, 7, 6) |
1456 (bits(machInst, 14, 12) << 2);
1457 const ArmShiftType type =
1458 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1459 return new Usat(machInst, rd, satImm, rn, imm, type);

--- 112 unchanged lines hidden ---