data.isa (12258:08990d24fe41) data.isa (12542:03cb745f9982)
1// Copyright (c) 2010,2017 ARM Limited
1// Copyright (c) 2010,2017-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated

--- 1184 unchanged lines hidden (view full) ---

1194 const bool enable = (bits(machInst, 4) == 0);
1195 const uint32_t mods = (bits(machInst, 2, 0) << 5) |
1196 ((enable ? 1 : 0) << 9);
1197 return new Cps(machInst, mods);
1198 }
1199 }
1200 case 0xa:
1201 {
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated

--- 1184 unchanged lines hidden (view full) ---

1194 const bool enable = (bits(machInst, 4) == 0);
1195 const uint32_t mods = (bits(machInst, 2, 0) << 5) |
1196 ((enable ? 1 : 0) << 9);
1197 return new Cps(machInst, mods);
1198 }
1199 }
1200 case 0xa:
1201 {
1202 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
1203 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
1204 switch (bits(machInst, 7, 6)) {
1205 case 0x0:
1206 return new Rev(machInst, rd, rm);
1207 case 0x1:
1208 return new Rev16(machInst, rd, rm);
1209 case 0x3:
1210 return new Revsh(machInst, rd, rm);
1211 default:
1212 break;
1202 const uint8_t op1 = bits(machInst, 7, 6);
1203 if (op1 == 0x2) {
1204 return new Hlt(machInst, bits(machInst, 5, 0));
1205 } else {
1206 IntRegIndex rd =
1207 (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
1208 IntRegIndex rm =
1209 (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
1210
1211 switch (op1) {
1212 case 0x0:
1213 return new Rev(machInst, rd, rm);
1214 case 0x1:
1215 return new Rev16(machInst, rd, rm);
1216 case 0x3:
1217 return new Revsh(machInst, rd, rm);
1218 default:
1219 break;
1220 }
1213 }
1214 }
1215 break;
1216 case 0x9:
1217 case 0xb:
1218 return new Cbnz(machInst,
1219 (bits(machInst, 9) << 6) |
1220 (bits(machInst, 7, 3) << 1),

--- 335 unchanged lines hidden --- 		1221 }
1222 }
1223 break;
1224 case 0x9:
1225 case 0xb:
1226 return new Cbnz(machInst,
1227 (bits(machInst, 9) << 6) |
1228 (bits(machInst, 7, 3) << 1),

--- 335 unchanged lines hidden ---