1// Copyright (c) 2010,2017-2018 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 62 unchanged lines hidden (view full) --- 71 } 72 return new Unknown(machInst); 73 } 74 ''' 75}}; 76 77def format ArmDataProcReg() {{ 78 pclr = ''' |
79 if (%(dest)s == INTREG_PC) { 80 return new %(className)ssRegPclr(machInst, %(dest)s, 81 %(op1)s, rm, imm5, 82 type); 83 } else |
84 ''' 85 instDecode = ''' 86 case %(opcode)#x: 87 if (immShift) { 88 if (setCc) { |
89 %(pclr)s { |
90 return new %(className)sRegCc(machInst, %(dest)s, 91 %(op1)s, rm, imm5, type); 92 } 93 } else { 94 return new %(className)sReg(machInst, %(dest)s, %(op1)s, 95 rm, imm5, type); 96 } 97 } else { --- 349 unchanged lines hidden (view full) --- 447 } 448 return new Unknown(machInst); 449 } 450 ''' 451}}; 452 453def format ArmDataProcImm() {{ 454 pclr = ''' |
455 if (%(dest)s == INTREG_PC) { 456 return new %(className)ssImmPclr(machInst, %(dest)s, 457 %(op1)s, imm, false); 458 } else |
459 ''' 460 adr = ''' |
461 if (%(op1)s == INTREG_PC) { 462 return new AdrImm(machInst, %(dest)s, %(add)s, 463 imm, false); 464 } else |
465 ''' 466 instDecode = ''' 467 case %(opcode)#x: 468 if (setCc) { |
469 %(pclr)s { |
470 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 471 imm, rotC); 472 } 473 } else { |
474 %(adr)s { |
475 return new %(className)sImm(machInst, %(dest)s, %(op1)s, 476 imm, rotC); 477 } 478 } 479 break; 480 ''' 481 482 def instCode(opcode, mnem, useDest = True, useOp1 = True): --- 5 unchanged lines hidden (view full) --- 488 if useOp1: 489 op1 = "rn" 490 else: 491 op1 = "INTREG_ZERO" 492 substDict = { "className": mnem.capitalize(), 493 "opcode": opcode, 494 "dest": dest, 495 "op1": op1, |
496 "adr": "" } |
497 if useDest: |
498 substDict["pclr"] = pclr % substDict 499 else: |
500 substDict["pclr"] = "" 501 return instDecode % substDict 502 503 def adrCode(opcode, mnem, add="1"): 504 global instDecode, pclr, adr 505 substDict = { "className": mnem.capitalize(), 506 "opcode": opcode, 507 "dest": "rd", 508 "op1": "rn", |
509 "add": add } |
510 substDict["pclr"] = pclr % substDict 511 substDict["adr"] = adr % substDict 512 return instDecode % substDict 513 514 decode_block = ''' 515 { 516 const bool setCc = (bits(machInst, 20) == 1); 517 const uint32_t unrotated = bits(machInst, 7, 0); --- 83 unchanged lines hidden (view full) --- 601 return new MovRegRegCc(machInst, rd, 602 INTREG_ZERO, rn, rm, ASR); 603 case 0x6: 604 return new MovRegReg(machInst, rd, 605 INTREG_ZERO, rn, rm, ROR); 606 case 0x7: 607 return new MovRegRegCc(machInst, rd, 608 INTREG_ZERO, rn, rm, ROR); |
609 default: 610 M5_UNREACHABLE; |
611 } 612 } else if (bits(op2, 3) == 0) { 613 return new Unknown(machInst); 614 } else { 615 const IntRegIndex rd = 616 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 617 const IntRegIndex rm = 618 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); --- 289 unchanged lines hidden (view full) --- 908 return new AddImmCc(machInst, rd, rn, imm3, true); 909 } 910 case 0x3: 911 if (machInst.itstateMask) { 912 return new SubImm(machInst, rd, rn, imm3, true); 913 } else { 914 return new SubImmCc(machInst, rd, rn, imm3, true); 915 } |
916 default: 917 M5_UNREACHABLE; |
918 } 919 case 0x4: 920 if (machInst.itstateMask) { 921 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false); 922 } else { 923 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 924 } 925 case 0x5: --- 5 unchanged lines hidden (view full) --- 931 return new AddImmCc(machInst, rd8, rd8, imm8, true); 932 } 933 case 0x7: 934 if (machInst.itstateMask) { 935 return new SubImm(machInst, rd8, rd8, imm8, true); 936 } else { 937 return new SubImmCc(machInst, rd8, rd8, imm8, true); 938 } |
939 default: 940 M5_UNREACHABLE; |
941 } 942 } 943 ''' 944}}; 945 946def format Thumb16DataProcessing() {{ 947 decode_block = ''' 948 { --- 87 unchanged lines hidden (view full) --- 1036 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 1037 } 1038 case 0xf: 1039 if (machInst.itstateMask) { 1040 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 1041 } else { 1042 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 1043 } |
1044 default: 1045 M5_UNREACHABLE; |
1046 } 1047 } 1048 ''' 1049}}; 1050 1051def format Thumb16SpecDataAndBx() {{ 1052 decode_block = ''' 1053 { --- 13 unchanged lines hidden (view full) --- 1067 return new BxReg(machInst, 1068 (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 1069 COND_UC); 1070 } else { 1071 return new BlxReg(machInst, 1072 (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 1073 COND_UC); 1074 } |
1075 default: 1076 M5_UNREACHABLE; |
1077 } 1078 } 1079 ''' 1080}}; 1081 1082def format Thumb16Adr() {{ 1083 decode_block = ''' 1084 { --- 84 unchanged lines hidden (view full) --- 1169 case 0x0: 1170 return new Sxth(machInst, rd, 0, rm); 1171 case 0x1: 1172 return new Sxtb(machInst, rd, 0, rm); 1173 case 0x2: 1174 return new Uxth(machInst, rd, 0, rm); 1175 case 0x3: 1176 return new Uxtb(machInst, rd, 0, rm); |
1177 default: 1178 M5_UNREACHABLE; |
1179 } 1180 } 1181 case 0x1: 1182 case 0x3: 1183 return new Cbz(machInst, 1184 (bits(machInst, 9) << 6) | 1185 (bits(machInst, 7, 3) << 1), 1186 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); --- 11 unchanged lines hidden (view full) --- 1198 if (opBits == 2) { 1199 return new Setend(machInst, bits(machInst, 3)); 1200 } else if (opBits == 3) { 1201 const bool enable = (bits(machInst, 4) == 0); 1202 const uint32_t mods = (bits(machInst, 2, 0) << 5) | 1203 ((enable ? 1 : 0) << 9); 1204 return new Cps(machInst, mods); 1205 } |
1206 return new Unknown(machInst); |
1207 } 1208 case 0xa: 1209 { 1210 const uint8_t op1 = bits(machInst, 7, 6); 1211 if (op1 == 0x2) { 1212 return new Hlt(machInst, bits(machInst, 5, 0)); 1213 } else { 1214 IntRegIndex rd = --- 195 unchanged lines hidden (view full) --- 1410 (bits(machInst, 19, 16) << 12); 1411 return new MovtImm(machInst, rd, rd, imm, true); 1412 } 1413 case 0x12: 1414 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 1415 const uint32_t satImm = bits(machInst, 4, 0); 1416 return new Ssat16(machInst, rd, satImm + 1, rn); 1417 } |
1418 M5_FALLTHROUGH; |
1419 case 0x10: 1420 { 1421 const uint32_t satImm = bits(machInst, 4, 0); 1422 const uint32_t imm = bits(machInst, 7, 6) | 1423 (bits(machInst, 14, 12) << 2); 1424 const ArmShiftType type = 1425 (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 1426 return new Ssat(machInst, rd, satImm + 1, rn, imm, type); --- 16 unchanged lines hidden (view full) --- 1443 return new Bfi(machInst, rd, rn, lsb, msb); 1444 } 1445 } 1446 case 0x1a: 1447 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 1448 const uint32_t satImm = bits(machInst, 4, 0); 1449 return new Usat16(machInst, rd, satImm, rn); 1450 } |
1451 M5_FALLTHROUGH; |
1452 case 0x18: 1453 { 1454 const uint32_t satImm = bits(machInst, 4, 0); 1455 const uint32_t imm = bits(machInst, 7, 6) | 1456 (bits(machInst, 14, 12) << 2); 1457 const ArmShiftType type = 1458 (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 1459 return new Usat(machInst, rd, satImm, rn, imm, type); --- 112 unchanged lines hidden --- |