1// Copyright (c) 2010,2017-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmMiscMedia() {{
39 decode_block = '''
40 {
41 const uint32_t op1 = bits(machInst, 22, 20);
42 const uint32_t op2 = bits(machInst, 7, 5);
43 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
44 const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
45 if (op1 == 0 && op2 == 0) {
46 const IntRegIndex rd =
47 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
48 const IntRegIndex rm =
49 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
50 if (ra == 0xf) {
51 return new Usad8(machInst, rd, rn, rm);
52 } else {
53 return new Usada8(machInst, rd, rn, rm, ra);
54 }
55 } else if (bits(op2, 1, 0) == 0x2) {
56 const uint32_t lsb = bits(machInst, 11, 7);
57 const uint32_t msb = lsb + bits(machInst, 20, 16);
58 if (bits(op1, 2, 1) == 0x3) {
59 return new Ubfx(machInst, ra, rn, lsb, msb);
60 } else if (bits(op1, 2, 1) == 0x1) {
61 return new Sbfx(machInst, ra, rn, lsb, msb);
62 }
63 } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) {
64 const uint32_t lsb = bits(machInst, 11, 7);
65 const uint32_t msb = bits(machInst, 20, 16);
66 if (rn == 0xf) {
67 return new Bfc(machInst, ra, ra, lsb, msb);
68 } else {
69 return new Bfi(machInst, ra, rn, lsb, msb);
70 }
71 }
72 return new Unknown(machInst);
73 }
74 '''
75}};
76
77def format ArmDataProcReg() {{
78 pclr = '''
| 1// Copyright (c) 2010,2017-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmMiscMedia() {{
39 decode_block = '''
40 {
41 const uint32_t op1 = bits(machInst, 22, 20);
42 const uint32_t op2 = bits(machInst, 7, 5);
43 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
44 const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
45 if (op1 == 0 && op2 == 0) {
46 const IntRegIndex rd =
47 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
48 const IntRegIndex rm =
49 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
50 if (ra == 0xf) {
51 return new Usad8(machInst, rd, rn, rm);
52 } else {
53 return new Usada8(machInst, rd, rn, rm, ra);
54 }
55 } else if (bits(op2, 1, 0) == 0x2) {
56 const uint32_t lsb = bits(machInst, 11, 7);
57 const uint32_t msb = lsb + bits(machInst, 20, 16);
58 if (bits(op1, 2, 1) == 0x3) {
59 return new Ubfx(machInst, ra, rn, lsb, msb);
60 } else if (bits(op1, 2, 1) == 0x1) {
61 return new Sbfx(machInst, ra, rn, lsb, msb);
62 }
63 } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) {
64 const uint32_t lsb = bits(machInst, 11, 7);
65 const uint32_t msb = bits(machInst, 20, 16);
66 if (rn == 0xf) {
67 return new Bfc(machInst, ra, ra, lsb, msb);
68 } else {
69 return new Bfi(machInst, ra, rn, lsb, msb);
70 }
71 }
72 return new Unknown(machInst);
73 }
74 '''
75}};
76
77def format ArmDataProcReg() {{
78 pclr = '''
|
79 return new %(className)ssRegPclr(machInst, %(dest)s,
80 %(op1)s, rm, imm5,
81 type);
| 79 if (%(dest)s == INTREG_PC) {
80 return new %(className)ssRegPclr(machInst, %(dest)s,
81 %(op1)s, rm, imm5,
82 type);
83 } else
|
82 '''
83 instDecode = '''
84 case %(opcode)#x:
85 if (immShift) {
86 if (setCc) {
| 84 '''
85 instDecode = '''
86 case %(opcode)#x:
87 if (immShift) {
88 if (setCc) {
|
87 if (%(dest)s == INTREG_PC) {
88 %(pclr)s
89 } else {
| 89 %(pclr)s {
|
90 return new %(className)sRegCc(machInst, %(dest)s,
91 %(op1)s, rm, imm5, type);
92 }
93 } else {
94 return new %(className)sReg(machInst, %(dest)s, %(op1)s,
95 rm, imm5, type);
96 }
97 } else {
98 if (setCc) {
99 return new %(className)sRegRegCc(machInst, %(dest)s,
100 %(op1)s, rm, rs, type);
101 } else {
102 return new %(className)sRegReg(machInst, %(dest)s,
103 %(op1)s, rm, rs, type);
104 }
105 }
106 break;
107 '''
108
109 def instCode(opcode, mnem, useDest = True, useOp1 = True):
110 global pclr
111 if useDest:
112 dest = "rd"
113 else:
114 dest = "INTREG_ZERO"
115 if useOp1:
116 op1 = "rn"
117 else:
118 op1 = "INTREG_ZERO"
119 global instDecode, pclrCode
120 substDict = { "className": mnem.capitalize(),
121 "opcode": opcode,
122 "dest": dest,
123 "op1": op1 }
124 if useDest:
125 substDict["pclr"] = pclr % substDict
126 else:
127 substDict["pclr"] = ""
128 return instDecode % substDict
129
130 decode_block = '''
131 {
132 const bool immShift = (bits(machInst, 4) == 0);
133 const bool setCc = (bits(machInst, 20) == 1);
134 const uint32_t imm5 = bits(machInst, 11, 7);
135 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
136 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
137 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
138 const IntRegIndex rm = (IntRegIndex)(uint32_t)RM;
139 const IntRegIndex rs = (IntRegIndex)(uint32_t)RS;
140 switch (OPCODE) {
141 '''
142 decode_block += instCode(0x0, "and")
143 decode_block += instCode(0x1, "eor")
144 decode_block += instCode(0x2, "sub")
145 decode_block += instCode(0x3, "rsb")
146 decode_block += instCode(0x4, "add")
147 decode_block += instCode(0x5, "adc")
148 decode_block += instCode(0x6, "sbc")
149 decode_block += instCode(0x7, "rsc")
150 decode_block += instCode(0x8, "tst", useDest = False)
151 decode_block += instCode(0x9, "teq", useDest = False)
152 decode_block += instCode(0xa, "cmp", useDest = False)
153 decode_block += instCode(0xb, "cmn", useDest = False)
154 decode_block += instCode(0xc, "orr")
155 decode_block += instCode(0xd, "mov", useOp1 = False)
156 decode_block += instCode(0xe, "bic")
157 decode_block += instCode(0xf, "mvn", useOp1 = False)
158 decode_block += '''
159 default:
160 return new Unknown(machInst);
161 }
162 }
163 '''
164}};
165
166def format ArmPackUnpackSatReverse() {{
167 decode_block = '''
168 {
169 const uint32_t op1 = bits(machInst, 22, 20);
170 const uint32_t a = bits(machInst, 19, 16);
171 const uint32_t op2 = bits(machInst, 7, 5);
172 if (bits(op2, 0) == 0) {
173 const IntRegIndex rn =
174 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
175 const IntRegIndex rd =
176 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
177 const uint32_t satImm = bits(machInst, 20, 16);
178 const uint32_t imm = bits(machInst, 11, 7);
179 const ArmShiftType type =
180 (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
181 if (op1 == 0) {
182 if (type) {
183 return new PkhtbReg(machInst, rd, (IntRegIndex)a,
184 rn, imm, type);
185 } else {
186 return new PkhbtReg(machInst, rd, (IntRegIndex)a,
187 rn, imm, type);
188 }
189 } else if (bits(op1, 2, 1) == 1) {
190 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
191 } else if (bits(op1, 2, 1) == 3) {
192 return new Usat(machInst, rd, satImm, rn, imm, type);
193 }
194 return new Unknown(machInst);
195 }
196 switch (op1) {
197 case 0x0:
198 {
199 const IntRegIndex rn =
200 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
201 const IntRegIndex rd =
202 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
203 const IntRegIndex rm =
204 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
205 if (op2 == 0x3) {
206 const uint32_t rotation =
207 (uint32_t)bits(machInst, 11, 10) << 3;
208 if (a == 0xf) {
209 return new Sxtb16(machInst, rd, rotation, rm);
210 } else {
211 return new Sxtab16(machInst, rd, rn, rm, rotation);
212 }
213 } else if (op2 == 0x5) {
214 return new Sel(machInst, rd, rn, rm);
215 }
216 }
217 break;
218 case 0x2:
219 if (op2 == 0x1) {
220 const IntRegIndex rn =
221 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
222 const IntRegIndex rd =
223 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
224 const uint32_t satImm = bits(machInst, 20, 16);
225 return new Ssat16(machInst, rd, satImm + 1, rn);
226 } else if (op2 == 0x3) {
227 const IntRegIndex rn =
228 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
229 const IntRegIndex rd =
230 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
231 const IntRegIndex rm =
232 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
233 const uint32_t rotation =
234 (uint32_t)bits(machInst, 11, 10) << 3;
235 if (a == 0xf) {
236 return new Sxtb(machInst, rd, rotation, rm);
237 } else {
238 return new Sxtab(machInst, rd, rn, rm, rotation);
239 }
240 }
241 break;
242 case 0x3:
243 if (op2 == 0x1) {
244 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
245 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
246 return new Rev(machInst, rd, rm);
247 } else if (op2 == 0x3) {
248 const IntRegIndex rn =
249 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
250 const IntRegIndex rd =
251 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
252 const IntRegIndex rm =
253 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
254 const uint32_t rotation =
255 (uint32_t)bits(machInst, 11, 10) << 3;
256 if (a == 0xf) {
257 return new Sxth(machInst, rd, rotation, rm);
258 } else {
259 return new Sxtah(machInst, rd, rn, rm, rotation);
260 }
261 } else if (op2 == 0x5) {
262 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
263 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
264 return new Rev16(machInst, rd, rm);
265 }
266 break;
267 case 0x4:
268 if (op2 == 0x3) {
269 const IntRegIndex rn =
270 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
271 const IntRegIndex rd =
272 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
273 const IntRegIndex rm =
274 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
275 const uint32_t rotation =
276 (uint32_t)bits(machInst, 11, 10) << 3;
277 if (a == 0xf) {
278 return new Uxtb16(machInst, rd, rotation, rm);
279 } else {
280 return new Uxtab16(machInst, rd, rn, rm, rotation);
281 }
282 }
283 break;
284 case 0x6:
285 if (op2 == 0x1) {
286 const IntRegIndex rn =
287 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
288 const IntRegIndex rd =
289 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
290 const uint32_t satImm = bits(machInst, 20, 16);
291 return new Usat16(machInst, rd, satImm, rn);
292 } else if (op2 == 0x3) {
293 const IntRegIndex rn =
294 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
295 const IntRegIndex rd =
296 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
297 const IntRegIndex rm =
298 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
299 const uint32_t rotation =
300 (uint32_t)bits(machInst, 11, 10) << 3;
301 if (a == 0xf) {
302 return new Uxtb(machInst, rd, rotation, rm);
303 } else {
304 return new Uxtab(machInst, rd, rn, rm, rotation);
305 }
306 }
307 break;
308 case 0x7:
309 {
310 const IntRegIndex rn =
311 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
312 const IntRegIndex rd =
313 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
314 const IntRegIndex rm =
315 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
316 if (op2 == 0x1) {
317 return new Rbit(machInst, rd, rm);
318 } else if (op2 == 0x3) {
319 const uint32_t rotation =
320 (uint32_t)bits(machInst, 11, 10) << 3;
321 if (a == 0xf) {
322 return new Uxth(machInst, rd, rotation, rm);
323 } else {
324 return new Uxtah(machInst, rd, rn, rm, rotation);
325 }
326 } else if (op2 == 0x5) {
327 return new Revsh(machInst, rd, rm);
328 }
329 }
330 break;
331 }
332 return new Unknown(machInst);
333 }
334 '''
335}};
336
337def format ArmParallelAddSubtract() {{
338 decode_block='''
339 {
340 const uint32_t op1 = bits(machInst, 21, 20);
341 const uint32_t op2 = bits(machInst, 7, 5);
342 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
343 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
344 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
345 if (bits(machInst, 22) == 0) {
346 switch (op1) {
347 case 0x1:
348 switch (op2) {
349 case 0x0:
350 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
351 case 0x1:
352 return new SasxRegCc(machInst, rd, rn, rm, 0, LSL);
353 case 0x2:
354 return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL);
355 case 0x3:
356 return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
357 case 0x4:
358 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
359 case 0x7:
360 return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
361 }
362 break;
363 case 0x2:
364 switch (op2) {
365 case 0x0:
366 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
367 case 0x1:
368 return new QasxReg(machInst, rd, rn, rm, 0, LSL);
369 case 0x2:
370 return new QsaxReg(machInst, rd, rn, rm, 0, LSL);
371 case 0x3:
372 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL);
373 case 0x4:
374 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
375 case 0x7:
376 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
377 }
378 break;
379 case 0x3:
380 switch (op2) {
381 case 0x0:
382 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL);
383 case 0x1:
384 return new ShasxReg(machInst, rd, rn, rm, 0, LSL);
385 case 0x2:
386 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL);
387 case 0x3:
388 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL);
389 case 0x4:
390 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL);
391 case 0x7:
392 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL);
393 }
394 break;
395 }
396 } else {
397 switch (op1) {
398 case 0x1:
399 switch (op2) {
400 case 0x0:
401 return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL);
402 case 0x1:
403 return new UasxRegCc(machInst, rd, rn, rm, 0, LSL);
404 case 0x2:
405 return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL);
406 case 0x3:
407 return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL);
408 case 0x4:
409 return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL);
410 case 0x7:
411 return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL);
412 }
413 break;
414 case 0x2:
415 switch (op2) {
416 case 0x0:
417 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
418 case 0x1:
419 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);
420 case 0x2:
421 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL);
422 case 0x3:
423 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL);
424 case 0x4:
425 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
426 case 0x7:
427 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
428 }
429 break;
430 case 0x3:
431 switch (op2) {
432 case 0x0:
433 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL);
434 case 0x1:
435 return new UhasxReg(machInst, rd, rn, rm, 0, LSL);
436 case 0x2:
437 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL);
438 case 0x3:
439 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL);
440 case 0x4:
441 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL);
442 case 0x7:
443 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL);
444 }
445 break;
446 }
447 }
448 return new Unknown(machInst);
449 }
450 '''
451}};
452
453def format ArmDataProcImm() {{
454 pclr = '''
| 90 return new %(className)sRegCc(machInst, %(dest)s,
91 %(op1)s, rm, imm5, type);
92 }
93 } else {
94 return new %(className)sReg(machInst, %(dest)s, %(op1)s,
95 rm, imm5, type);
96 }
97 } else {
98 if (setCc) {
99 return new %(className)sRegRegCc(machInst, %(dest)s,
100 %(op1)s, rm, rs, type);
101 } else {
102 return new %(className)sRegReg(machInst, %(dest)s,
103 %(op1)s, rm, rs, type);
104 }
105 }
106 break;
107 '''
108
109 def instCode(opcode, mnem, useDest = True, useOp1 = True):
110 global pclr
111 if useDest:
112 dest = "rd"
113 else:
114 dest = "INTREG_ZERO"
115 if useOp1:
116 op1 = "rn"
117 else:
118 op1 = "INTREG_ZERO"
119 global instDecode, pclrCode
120 substDict = { "className": mnem.capitalize(),
121 "opcode": opcode,
122 "dest": dest,
123 "op1": op1 }
124 if useDest:
125 substDict["pclr"] = pclr % substDict
126 else:
127 substDict["pclr"] = ""
128 return instDecode % substDict
129
130 decode_block = '''
131 {
132 const bool immShift = (bits(machInst, 4) == 0);
133 const bool setCc = (bits(machInst, 20) == 1);
134 const uint32_t imm5 = bits(machInst, 11, 7);
135 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
136 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
137 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
138 const IntRegIndex rm = (IntRegIndex)(uint32_t)RM;
139 const IntRegIndex rs = (IntRegIndex)(uint32_t)RS;
140 switch (OPCODE) {
141 '''
142 decode_block += instCode(0x0, "and")
143 decode_block += instCode(0x1, "eor")
144 decode_block += instCode(0x2, "sub")
145 decode_block += instCode(0x3, "rsb")
146 decode_block += instCode(0x4, "add")
147 decode_block += instCode(0x5, "adc")
148 decode_block += instCode(0x6, "sbc")
149 decode_block += instCode(0x7, "rsc")
150 decode_block += instCode(0x8, "tst", useDest = False)
151 decode_block += instCode(0x9, "teq", useDest = False)
152 decode_block += instCode(0xa, "cmp", useDest = False)
153 decode_block += instCode(0xb, "cmn", useDest = False)
154 decode_block += instCode(0xc, "orr")
155 decode_block += instCode(0xd, "mov", useOp1 = False)
156 decode_block += instCode(0xe, "bic")
157 decode_block += instCode(0xf, "mvn", useOp1 = False)
158 decode_block += '''
159 default:
160 return new Unknown(machInst);
161 }
162 }
163 '''
164}};
165
166def format ArmPackUnpackSatReverse() {{
167 decode_block = '''
168 {
169 const uint32_t op1 = bits(machInst, 22, 20);
170 const uint32_t a = bits(machInst, 19, 16);
171 const uint32_t op2 = bits(machInst, 7, 5);
172 if (bits(op2, 0) == 0) {
173 const IntRegIndex rn =
174 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
175 const IntRegIndex rd =
176 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
177 const uint32_t satImm = bits(machInst, 20, 16);
178 const uint32_t imm = bits(machInst, 11, 7);
179 const ArmShiftType type =
180 (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
181 if (op1 == 0) {
182 if (type) {
183 return new PkhtbReg(machInst, rd, (IntRegIndex)a,
184 rn, imm, type);
185 } else {
186 return new PkhbtReg(machInst, rd, (IntRegIndex)a,
187 rn, imm, type);
188 }
189 } else if (bits(op1, 2, 1) == 1) {
190 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
191 } else if (bits(op1, 2, 1) == 3) {
192 return new Usat(machInst, rd, satImm, rn, imm, type);
193 }
194 return new Unknown(machInst);
195 }
196 switch (op1) {
197 case 0x0:
198 {
199 const IntRegIndex rn =
200 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
201 const IntRegIndex rd =
202 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
203 const IntRegIndex rm =
204 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
205 if (op2 == 0x3) {
206 const uint32_t rotation =
207 (uint32_t)bits(machInst, 11, 10) << 3;
208 if (a == 0xf) {
209 return new Sxtb16(machInst, rd, rotation, rm);
210 } else {
211 return new Sxtab16(machInst, rd, rn, rm, rotation);
212 }
213 } else if (op2 == 0x5) {
214 return new Sel(machInst, rd, rn, rm);
215 }
216 }
217 break;
218 case 0x2:
219 if (op2 == 0x1) {
220 const IntRegIndex rn =
221 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
222 const IntRegIndex rd =
223 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
224 const uint32_t satImm = bits(machInst, 20, 16);
225 return new Ssat16(machInst, rd, satImm + 1, rn);
226 } else if (op2 == 0x3) {
227 const IntRegIndex rn =
228 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
229 const IntRegIndex rd =
230 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
231 const IntRegIndex rm =
232 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
233 const uint32_t rotation =
234 (uint32_t)bits(machInst, 11, 10) << 3;
235 if (a == 0xf) {
236 return new Sxtb(machInst, rd, rotation, rm);
237 } else {
238 return new Sxtab(machInst, rd, rn, rm, rotation);
239 }
240 }
241 break;
242 case 0x3:
243 if (op2 == 0x1) {
244 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
245 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
246 return new Rev(machInst, rd, rm);
247 } else if (op2 == 0x3) {
248 const IntRegIndex rn =
249 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
250 const IntRegIndex rd =
251 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
252 const IntRegIndex rm =
253 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
254 const uint32_t rotation =
255 (uint32_t)bits(machInst, 11, 10) << 3;
256 if (a == 0xf) {
257 return new Sxth(machInst, rd, rotation, rm);
258 } else {
259 return new Sxtah(machInst, rd, rn, rm, rotation);
260 }
261 } else if (op2 == 0x5) {
262 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
263 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
264 return new Rev16(machInst, rd, rm);
265 }
266 break;
267 case 0x4:
268 if (op2 == 0x3) {
269 const IntRegIndex rn =
270 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
271 const IntRegIndex rd =
272 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
273 const IntRegIndex rm =
274 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
275 const uint32_t rotation =
276 (uint32_t)bits(machInst, 11, 10) << 3;
277 if (a == 0xf) {
278 return new Uxtb16(machInst, rd, rotation, rm);
279 } else {
280 return new Uxtab16(machInst, rd, rn, rm, rotation);
281 }
282 }
283 break;
284 case 0x6:
285 if (op2 == 0x1) {
286 const IntRegIndex rn =
287 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
288 const IntRegIndex rd =
289 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
290 const uint32_t satImm = bits(machInst, 20, 16);
291 return new Usat16(machInst, rd, satImm, rn);
292 } else if (op2 == 0x3) {
293 const IntRegIndex rn =
294 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
295 const IntRegIndex rd =
296 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
297 const IntRegIndex rm =
298 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
299 const uint32_t rotation =
300 (uint32_t)bits(machInst, 11, 10) << 3;
301 if (a == 0xf) {
302 return new Uxtb(machInst, rd, rotation, rm);
303 } else {
304 return new Uxtab(machInst, rd, rn, rm, rotation);
305 }
306 }
307 break;
308 case 0x7:
309 {
310 const IntRegIndex rn =
311 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
312 const IntRegIndex rd =
313 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
314 const IntRegIndex rm =
315 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
316 if (op2 == 0x1) {
317 return new Rbit(machInst, rd, rm);
318 } else if (op2 == 0x3) {
319 const uint32_t rotation =
320 (uint32_t)bits(machInst, 11, 10) << 3;
321 if (a == 0xf) {
322 return new Uxth(machInst, rd, rotation, rm);
323 } else {
324 return new Uxtah(machInst, rd, rn, rm, rotation);
325 }
326 } else if (op2 == 0x5) {
327 return new Revsh(machInst, rd, rm);
328 }
329 }
330 break;
331 }
332 return new Unknown(machInst);
333 }
334 '''
335}};
336
337def format ArmParallelAddSubtract() {{
338 decode_block='''
339 {
340 const uint32_t op1 = bits(machInst, 21, 20);
341 const uint32_t op2 = bits(machInst, 7, 5);
342 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
343 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
344 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
345 if (bits(machInst, 22) == 0) {
346 switch (op1) {
347 case 0x1:
348 switch (op2) {
349 case 0x0:
350 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
351 case 0x1:
352 return new SasxRegCc(machInst, rd, rn, rm, 0, LSL);
353 case 0x2:
354 return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL);
355 case 0x3:
356 return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
357 case 0x4:
358 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
359 case 0x7:
360 return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
361 }
362 break;
363 case 0x2:
364 switch (op2) {
365 case 0x0:
366 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
367 case 0x1:
368 return new QasxReg(machInst, rd, rn, rm, 0, LSL);
369 case 0x2:
370 return new QsaxReg(machInst, rd, rn, rm, 0, LSL);
371 case 0x3:
372 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL);
373 case 0x4:
374 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
375 case 0x7:
376 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
377 }
378 break;
379 case 0x3:
380 switch (op2) {
381 case 0x0:
382 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL);
383 case 0x1:
384 return new ShasxReg(machInst, rd, rn, rm, 0, LSL);
385 case 0x2:
386 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL);
387 case 0x3:
388 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL);
389 case 0x4:
390 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL);
391 case 0x7:
392 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL);
393 }
394 break;
395 }
396 } else {
397 switch (op1) {
398 case 0x1:
399 switch (op2) {
400 case 0x0:
401 return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL);
402 case 0x1:
403 return new UasxRegCc(machInst, rd, rn, rm, 0, LSL);
404 case 0x2:
405 return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL);
406 case 0x3:
407 return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL);
408 case 0x4:
409 return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL);
410 case 0x7:
411 return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL);
412 }
413 break;
414 case 0x2:
415 switch (op2) {
416 case 0x0:
417 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
418 case 0x1:
419 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);
420 case 0x2:
421 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL);
422 case 0x3:
423 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL);
424 case 0x4:
425 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
426 case 0x7:
427 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
428 }
429 break;
430 case 0x3:
431 switch (op2) {
432 case 0x0:
433 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL);
434 case 0x1:
435 return new UhasxReg(machInst, rd, rn, rm, 0, LSL);
436 case 0x2:
437 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL);
438 case 0x3:
439 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL);
440 case 0x4:
441 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL);
442 case 0x7:
443 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL);
444 }
445 break;
446 }
447 }
448 return new Unknown(machInst);
449 }
450 '''
451}};
452
453def format ArmDataProcImm() {{
454 pclr = '''
|
455 return new %(className)ssImmPclr(machInst, %(dest)s,
456 %(op1)s, imm, false);
| 455 if (%(dest)s == INTREG_PC) {
456 return new %(className)ssImmPclr(machInst, %(dest)s,
457 %(op1)s, imm, false);
458 } else
|
457 '''
458 adr = '''
| 459 '''
460 adr = '''
|
459 return new AdrImm(machInst, %(dest)s, %(add)s,
460 imm, false);
| 461 if (%(op1)s == INTREG_PC) {
462 return new AdrImm(machInst, %(dest)s, %(add)s,
463 imm, false);
464 } else
|
461 '''
462 instDecode = '''
463 case %(opcode)#x:
464 if (setCc) {
| 465 '''
466 instDecode = '''
467 case %(opcode)#x:
468 if (setCc) {
|
465 if (%(pclrInst)s && %(dest)s == INTREG_PC) {
466 %(pclr)s
467 } else {
| 469 %(pclr)s {
|
468 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
469 imm, rotC);
470 }
471 } else {
| 470 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
471 imm, rotC);
472 }
473 } else {
|
472 if (%(adrInst)s && %(op1)s == INTREG_PC) {
473 %(adr)s
474 } else {
| 474 %(adr)s {
|
475 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
476 imm, rotC);
477 }
478 }
479 break;
480 '''
481
482 def instCode(opcode, mnem, useDest = True, useOp1 = True):
483 global instDecode, pclr, adr
484 if useDest:
485 dest = "rd"
486 else:
487 dest = "INTREG_ZERO"
488 if useOp1:
489 op1 = "rn"
490 else:
491 op1 = "INTREG_ZERO"
492 substDict = { "className": mnem.capitalize(),
493 "opcode": opcode,
494 "dest": dest,
495 "op1": op1,
| 475 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
476 imm, rotC);
477 }
478 }
479 break;
480 '''
481
482 def instCode(opcode, mnem, useDest = True, useOp1 = True):
483 global instDecode, pclr, adr
484 if useDest:
485 dest = "rd"
486 else:
487 dest = "INTREG_ZERO"
488 if useOp1:
489 op1 = "rn"
490 else:
491 op1 = "INTREG_ZERO"
492 substDict = { "className": mnem.capitalize(),
493 "opcode": opcode,
494 "dest": dest,
495 "op1": op1,
|
496 "adr": "",
497 "adrInst": "false" }
| 496 "adr": "" }
|
498 if useDest:
| 497 if useDest:
|
499 substDict["pclrInst"] = "true"
| |
500 substDict["pclr"] = pclr % substDict
501 else:
| 498 substDict["pclr"] = pclr % substDict
499 else:
|
502 substDict["pclrInst"] = "false"
| |
503 substDict["pclr"] = ""
504 return instDecode % substDict
505
506 def adrCode(opcode, mnem, add="1"):
507 global instDecode, pclr, adr
508 substDict = { "className": mnem.capitalize(),
509 "opcode": opcode,
510 "dest": "rd",
511 "op1": "rn",
| 500 substDict["pclr"] = ""
501 return instDecode % substDict
502
503 def adrCode(opcode, mnem, add="1"):
504 global instDecode, pclr, adr
505 substDict = { "className": mnem.capitalize(),
506 "opcode": opcode,
507 "dest": "rd",
508 "op1": "rn",
|
512 "add": add,
513 "pclrInst": "true",
514 "adrInst": "true" }
| 509 "add": add }
|
515 substDict["pclr"] = pclr % substDict
516 substDict["adr"] = adr % substDict
517 return instDecode % substDict
518
519 decode_block = '''
520 {
521 const bool setCc = (bits(machInst, 20) == 1);
522 const uint32_t unrotated = bits(machInst, 7, 0);
523 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
524 const bool rotC = (rotation != 0);
525 const uint32_t imm = rotate_imm(unrotated, rotation);
526 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
527 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
528 switch (OPCODE) {
529 '''
530 decode_block += instCode(0x0, "and")
531 decode_block += instCode(0x1, "eor")
532 decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0")
533 decode_block += instCode(0x3, "rsb")
534 decode_block += adrCode(0x4, "add", add="(IntRegIndex)1")
535 decode_block += instCode(0x5, "adc")
536 decode_block += instCode(0x6, "sbc")
537 decode_block += instCode(0x7, "rsc")
538 decode_block += instCode(0x8, "tst", useDest = False)
539 decode_block += instCode(0x9, "teq", useDest = False)
540 decode_block += instCode(0xa, "cmp", useDest = False)
541 decode_block += instCode(0xb, "cmn", useDest = False)
542 decode_block += instCode(0xc, "orr")
543 decode_block += instCode(0xd, "mov", useOp1 = False)
544 decode_block += instCode(0xe, "bic")
545 decode_block += instCode(0xf, "mvn", useOp1 = False)
546 decode_block += '''
547 default:
548 return new Unknown(machInst);
549 }
550 }
551 '''
552}};
553
554def format ArmSatAddSub() {{
555 decode_block = '''
556 {
557 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
558 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
559 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
560 switch (OPCODE) {
561 case 0x8:
562 return new QaddRegCc(machInst, rd, rm, rn, 0, LSL);
563 case 0x9:
564 return new QsubRegCc(machInst, rd, rm, rn, 0, LSL);
565 case 0xa:
566 return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL);
567 case 0xb:
568 return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
569 default:
570 return new Unknown(machInst);
571 }
572 }
573 '''
574}};
575
576def format Thumb32DataProcReg() {{
577 decode_block = '''
578 {
579 const uint32_t op1 = bits(machInst, 23, 20);
580 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
581 const uint32_t op2 = bits(machInst, 7, 4);
582 if (bits(machInst, 15, 12) != 0xf) {
583 return new Unknown(machInst);
584 }
585 if (bits(op1, 3) != 1) {
586 if (op2 == 0) {
587 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
588 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
589 switch (bits(op1, 2, 0)) {
590 case 0x0:
591 return new MovRegReg(machInst, rd,
592 INTREG_ZERO, rn, rm, LSL);
593 case 0x1:
594 return new MovRegRegCc(machInst, rd,
595 INTREG_ZERO, rn, rm, LSL);
596 case 0x2:
597 return new MovRegReg(machInst, rd,
598 INTREG_ZERO, rn, rm, LSR);
599 case 0x3:
600 return new MovRegRegCc(machInst, rd,
601 INTREG_ZERO, rn, rm, LSR);
602 case 0x4:
603 return new MovRegReg(machInst, rd,
604 INTREG_ZERO, rn, rm, ASR);
605 case 0x5:
606 return new MovRegRegCc(machInst, rd,
607 INTREG_ZERO, rn, rm, ASR);
608 case 0x6:
609 return new MovRegReg(machInst, rd,
610 INTREG_ZERO, rn, rm, ROR);
611 case 0x7:
612 return new MovRegRegCc(machInst, rd,
613 INTREG_ZERO, rn, rm, ROR);
| 510 substDict["pclr"] = pclr % substDict
511 substDict["adr"] = adr % substDict
512 return instDecode % substDict
513
514 decode_block = '''
515 {
516 const bool setCc = (bits(machInst, 20) == 1);
517 const uint32_t unrotated = bits(machInst, 7, 0);
518 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
519 const bool rotC = (rotation != 0);
520 const uint32_t imm = rotate_imm(unrotated, rotation);
521 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
522 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
523 switch (OPCODE) {
524 '''
525 decode_block += instCode(0x0, "and")
526 decode_block += instCode(0x1, "eor")
527 decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0")
528 decode_block += instCode(0x3, "rsb")
529 decode_block += adrCode(0x4, "add", add="(IntRegIndex)1")
530 decode_block += instCode(0x5, "adc")
531 decode_block += instCode(0x6, "sbc")
532 decode_block += instCode(0x7, "rsc")
533 decode_block += instCode(0x8, "tst", useDest = False)
534 decode_block += instCode(0x9, "teq", useDest = False)
535 decode_block += instCode(0xa, "cmp", useDest = False)
536 decode_block += instCode(0xb, "cmn", useDest = False)
537 decode_block += instCode(0xc, "orr")
538 decode_block += instCode(0xd, "mov", useOp1 = False)
539 decode_block += instCode(0xe, "bic")
540 decode_block += instCode(0xf, "mvn", useOp1 = False)
541 decode_block += '''
542 default:
543 return new Unknown(machInst);
544 }
545 }
546 '''
547}};
548
549def format ArmSatAddSub() {{
550 decode_block = '''
551 {
552 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
553 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
554 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
555 switch (OPCODE) {
556 case 0x8:
557 return new QaddRegCc(machInst, rd, rm, rn, 0, LSL);
558 case 0x9:
559 return new QsubRegCc(machInst, rd, rm, rn, 0, LSL);
560 case 0xa:
561 return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL);
562 case 0xb:
563 return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
564 default:
565 return new Unknown(machInst);
566 }
567 }
568 '''
569}};
570
571def format Thumb32DataProcReg() {{
572 decode_block = '''
573 {
574 const uint32_t op1 = bits(machInst, 23, 20);
575 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
576 const uint32_t op2 = bits(machInst, 7, 4);
577 if (bits(machInst, 15, 12) != 0xf) {
578 return new Unknown(machInst);
579 }
580 if (bits(op1, 3) != 1) {
581 if (op2 == 0) {
582 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
583 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
584 switch (bits(op1, 2, 0)) {
585 case 0x0:
586 return new MovRegReg(machInst, rd,
587 INTREG_ZERO, rn, rm, LSL);
588 case 0x1:
589 return new MovRegRegCc(machInst, rd,
590 INTREG_ZERO, rn, rm, LSL);
591 case 0x2:
592 return new MovRegReg(machInst, rd,
593 INTREG_ZERO, rn, rm, LSR);
594 case 0x3:
595 return new MovRegRegCc(machInst, rd,
596 INTREG_ZERO, rn, rm, LSR);
597 case 0x4:
598 return new MovRegReg(machInst, rd,
599 INTREG_ZERO, rn, rm, ASR);
600 case 0x5:
601 return new MovRegRegCc(machInst, rd,
602 INTREG_ZERO, rn, rm, ASR);
603 case 0x6:
604 return new MovRegReg(machInst, rd,
605 INTREG_ZERO, rn, rm, ROR);
606 case 0x7:
607 return new MovRegRegCc(machInst, rd,
608 INTREG_ZERO, rn, rm, ROR);
|
| 609 default:
610 M5_UNREACHABLE;
|
614 }
615 } else if (bits(op2, 3) == 0) {
616 return new Unknown(machInst);
617 } else {
618 const IntRegIndex rd =
619 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
620 const IntRegIndex rm =
621 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
622 const uint32_t rotation =
623 (uint32_t)bits(machInst, 5, 4) << 3;
624 switch (bits(op1, 2, 0)) {
625 case 0x0:
626 if (rn == 0xf) {
627 return new Sxth(machInst, rd, rotation, rm);
628 } else {
629 return new Sxtah(machInst, rd, rn, rm, rotation);
630 }
631 case 0x1:
632 if (rn == 0xf) {
633 return new Uxth(machInst, rd, rotation, rm);
634 } else {
635 return new Uxtah(machInst, rd, rn, rm, rotation);
636 }
637 case 0x2:
638 if (rn == 0xf) {
639 return new Sxtb16(machInst, rd, rotation, rm);
640 } else {
641 return new Sxtab16(machInst, rd, rn, rm, rotation);
642 }
643 case 0x3:
644 if (rn == 0xf) {
645 return new Uxtb16(machInst, rd, rotation, rm);
646 } else {
647 return new Uxtab16(machInst, rd, rn, rm, rotation);
648 }
649 case 0x4:
650 if (rn == 0xf) {
651 return new Sxtb(machInst, rd, rotation, rm);
652 } else {
653 return new Sxtab(machInst, rd, rn, rm, rotation);
654 }
655 case 0x5:
656 if (rn == 0xf) {
657 return new Uxtb(machInst, rd, rotation, rm);
658 } else {
659 return new Uxtab(machInst, rd, rn, rm, rotation);
660 }
661 default:
662 return new Unknown(machInst);
663 }
664 }
665 } else {
666 if (bits(op2, 3) == 0) {
667 const IntRegIndex rd =
668 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
669 const IntRegIndex rm =
670 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
671 if (bits(op2, 2) == 0x0) {
672 const uint32_t op1 = bits(machInst, 22, 20);
673 const uint32_t op2 = bits(machInst, 5, 4);
674 switch (op2) {
675 case 0x0:
676 switch (op1) {
677 case 0x1:
678 return new Sadd16RegCc(machInst, rd,
679 rn, rm, 0, LSL);
680 case 0x2:
681 return new SasxRegCc(machInst, rd,
682 rn, rm, 0, LSL);
683 case 0x6:
684 return new SsaxRegCc(machInst, rd,
685 rn, rm, 0, LSL);
686 case 0x5:
687 return new Ssub16RegCc(machInst, rd,
688 rn, rm, 0, LSL);
689 case 0x0:
690 return new Sadd8RegCc(machInst, rd,
691 rn, rm, 0, LSL);
692 case 0x4:
693 return new Ssub8RegCc(machInst, rd,
694 rn, rm, 0, LSL);
695 }
696 break;
697 case 0x1:
698 switch (op1) {
699 case 0x1:
700 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
701 case 0x2:
702 return new QasxReg(machInst, rd, rn, rm, 0, LSL);
703 case 0x6:
704 return new QsaxReg(machInst, rd, rn, rm, 0, LSL);
705 case 0x5:
706 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL);
707 case 0x0:
708 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
709 case 0x4:
710 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
711 }
712 break;
713 case 0x2:
714 switch (op1) {
715 case 0x1:
716 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL);
717 case 0x2:
718 return new ShasxReg(machInst, rd, rn, rm, 0, LSL);
719 case 0x6:
720 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL);
721 case 0x5:
722 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL);
723 case 0x0:
724 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL);
725 case 0x4:
726 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL);
727 }
728 break;
729 }
730 } else {
731 const uint32_t op1 = bits(machInst, 22, 20);
732 const uint32_t op2 = bits(machInst, 5, 4);
733 switch (op2) {
734 case 0x0:
735 switch (op1) {
736 case 0x1:
737 return new Uadd16RegCc(machInst, rd,
738 rn, rm, 0, LSL);
739 case 0x2:
740 return new UasxRegCc(machInst, rd,
741 rn, rm, 0, LSL);
742 case 0x6:
743 return new UsaxRegCc(machInst, rd,
744 rn, rm, 0, LSL);
745 case 0x5:
746 return new Usub16RegCc(machInst, rd,
747 rn, rm, 0, LSL);
748 case 0x0:
749 return new Uadd8RegCc(machInst, rd,
750 rn, rm, 0, LSL);
751 case 0x4:
752 return new Usub8RegCc(machInst, rd,
753 rn, rm, 0, LSL);
754 }
755 break;
756 case 0x1:
757 switch (op1) {
758 case 0x1:
759 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
760 case 0x2:
761 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);
762 case 0x6:
763 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL);
764 case 0x5:
765 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL);
766 case 0x0:
767 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
768 case 0x4:
769 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
770 }
771 break;
772 case 0x2:
773 switch (op1) {
774 case 0x1:
775 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL);
776 case 0x2:
777 return new UhasxReg(machInst, rd, rn, rm, 0, LSL);
778 case 0x6:
779 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL);
780 case 0x5:
781 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL);
782 case 0x0:
783 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL);
784 case 0x4:
785 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL);
786 }
787 break;
788 }
789 }
790 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) {
791 const uint32_t op1 = bits(machInst, 22, 20);
792 const uint32_t op2 = bits(machInst, 5, 4);
793 const IntRegIndex rd =
794 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
795 const IntRegIndex rm =
796 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
797 switch (op1) {
798 case 0x0:
799 switch (op2) {
800 case 0x0:
801 return new QaddRegCc(machInst, rd,
802 rm, rn, 0, LSL);
803 case 0x1:
804 return new QdaddRegCc(machInst, rd,
805 rm, rn, 0, LSL);
806 case 0x2:
807 return new QsubRegCc(machInst, rd,
808 rm, rn, 0, LSL);
809 case 0x3:
810 return new QdsubRegCc(machInst, rd,
811 rm, rn, 0, LSL);
812 }
813 break;
814 case 0x1:
815 switch (op2) {
816 case 0x0:
817 return new Rev(machInst, rd, rn);
818 case 0x1:
819 return new Rev16(machInst, rd, rn);
820 case 0x2:
821 return new Rbit(machInst, rd, rm);
822 case 0x3:
823 return new Revsh(machInst, rd, rn);
824 }
825 break;
826 case 0x2:
827 if (op2 == 0) {
828 return new Sel(machInst, rd, rn, rm);
829 }
830 break;
831 case 0x3:
832 if (op2 == 0) {
833 return new Clz(machInst, rd, rm);
834 }
835 break;
836 case 0x4:
837 switch (op2) {
838 case 0x0:
839 return new Crc32b(machInst, rd, rn, rm);
840 case 0x1:
841 return new Crc32h(machInst, rd, rn, rm);
842 case 0x2:
843 return new Crc32w(machInst, rd, rn, rm);
844 }
845 break;
846 case 0x5:
847 switch (op2) {
848 case 0x0:
849 return new Crc32cb(machInst, rd, rn, rm);
850 case 0x1:
851 return new Crc32ch(machInst, rd, rn, rm);
852 case 0x2:
853 return new Crc32cw(machInst, rd, rn, rm);
854 }
855 break;
856 }
857 }
858 return new Unknown(machInst);
859 }
860 }
861 '''
862}};
863
864def format Thumb16ShiftAddSubMoveCmp() {{
865 decode_block = '''
866 {
867 const uint32_t imm5 = bits(machInst, 10, 6);
868 const uint32_t imm3 = bits(machInst, 8, 6);
869 const uint32_t imm8 = bits(machInst, 7, 0);
870 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
871 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
872 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
873 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
874 switch (bits(machInst, 13, 11)) {
875 case 0x0: // lsl
876 if (machInst.itstateMask) {
877 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
878 } else {
879 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
880 }
881 case 0x1: // lsr
882 if (machInst.itstateMask) {
883 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
884 } else {
885 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
886 }
887 case 0x2: // asr
888 if (machInst.itstateMask) {
889 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
890 } else {
891 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
892 }
893 case 0x3:
894 switch (bits(machInst, 10, 9)) {
895 case 0x0:
896 if (machInst.itstateMask) {
897 return new AddReg(machInst, rd, rn, rm, 0, LSL);
898 } else {
899 return new AddRegCc(machInst, rd, rn, rm, 0, LSL);
900 }
901 case 0x1:
902 if (machInst.itstateMask) {
903 return new SubReg(machInst, rd, rn, rm, 0, LSL);
904 } else {
905 return new SubRegCc(machInst, rd, rn, rm, 0, LSL);
906 }
907 case 0x2:
908 if (machInst.itstateMask) {
909 return new AddImm(machInst, rd, rn, imm3, true);
910 } else {
911 return new AddImmCc(machInst, rd, rn, imm3, true);
912 }
913 case 0x3:
914 if (machInst.itstateMask) {
915 return new SubImm(machInst, rd, rn, imm3, true);
916 } else {
917 return new SubImmCc(machInst, rd, rn, imm3, true);
918 }
| 611 }
612 } else if (bits(op2, 3) == 0) {
613 return new Unknown(machInst);
614 } else {
615 const IntRegIndex rd =
616 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
617 const IntRegIndex rm =
618 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
619 const uint32_t rotation =
620 (uint32_t)bits(machInst, 5, 4) << 3;
621 switch (bits(op1, 2, 0)) {
622 case 0x0:
623 if (rn == 0xf) {
624 return new Sxth(machInst, rd, rotation, rm);
625 } else {
626 return new Sxtah(machInst, rd, rn, rm, rotation);
627 }
628 case 0x1:
629 if (rn == 0xf) {
630 return new Uxth(machInst, rd, rotation, rm);
631 } else {
632 return new Uxtah(machInst, rd, rn, rm, rotation);
633 }
634 case 0x2:
635 if (rn == 0xf) {
636 return new Sxtb16(machInst, rd, rotation, rm);
637 } else {
638 return new Sxtab16(machInst, rd, rn, rm, rotation);
639 }
640 case 0x3:
641 if (rn == 0xf) {
642 return new Uxtb16(machInst, rd, rotation, rm);
643 } else {
644 return new Uxtab16(machInst, rd, rn, rm, rotation);
645 }
646 case 0x4:
647 if (rn == 0xf) {
648 return new Sxtb(machInst, rd, rotation, rm);
649 } else {
650 return new Sxtab(machInst, rd, rn, rm, rotation);
651 }
652 case 0x5:
653 if (rn == 0xf) {
654 return new Uxtb(machInst, rd, rotation, rm);
655 } else {
656 return new Uxtab(machInst, rd, rn, rm, rotation);
657 }
658 default:
659 return new Unknown(machInst);
660 }
661 }
662 } else {
663 if (bits(op2, 3) == 0) {
664 const IntRegIndex rd =
665 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
666 const IntRegIndex rm =
667 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
668 if (bits(op2, 2) == 0x0) {
669 const uint32_t op1 = bits(machInst, 22, 20);
670 const uint32_t op2 = bits(machInst, 5, 4);
671 switch (op2) {
672 case 0x0:
673 switch (op1) {
674 case 0x1:
675 return new Sadd16RegCc(machInst, rd,
676 rn, rm, 0, LSL);
677 case 0x2:
678 return new SasxRegCc(machInst, rd,
679 rn, rm, 0, LSL);
680 case 0x6:
681 return new SsaxRegCc(machInst, rd,
682 rn, rm, 0, LSL);
683 case 0x5:
684 return new Ssub16RegCc(machInst, rd,
685 rn, rm, 0, LSL);
686 case 0x0:
687 return new Sadd8RegCc(machInst, rd,
688 rn, rm, 0, LSL);
689 case 0x4:
690 return new Ssub8RegCc(machInst, rd,
691 rn, rm, 0, LSL);
692 }
693 break;
694 case 0x1:
695 switch (op1) {
696 case 0x1:
697 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
698 case 0x2:
699 return new QasxReg(machInst, rd, rn, rm, 0, LSL);
700 case 0x6:
701 return new QsaxReg(machInst, rd, rn, rm, 0, LSL);
702 case 0x5:
703 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL);
704 case 0x0:
705 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
706 case 0x4:
707 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
708 }
709 break;
710 case 0x2:
711 switch (op1) {
712 case 0x1:
713 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL);
714 case 0x2:
715 return new ShasxReg(machInst, rd, rn, rm, 0, LSL);
716 case 0x6:
717 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL);
718 case 0x5:
719 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL);
720 case 0x0:
721 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL);
722 case 0x4:
723 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL);
724 }
725 break;
726 }
727 } else {
728 const uint32_t op1 = bits(machInst, 22, 20);
729 const uint32_t op2 = bits(machInst, 5, 4);
730 switch (op2) {
731 case 0x0:
732 switch (op1) {
733 case 0x1:
734 return new Uadd16RegCc(machInst, rd,
735 rn, rm, 0, LSL);
736 case 0x2:
737 return new UasxRegCc(machInst, rd,
738 rn, rm, 0, LSL);
739 case 0x6:
740 return new UsaxRegCc(machInst, rd,
741 rn, rm, 0, LSL);
742 case 0x5:
743 return new Usub16RegCc(machInst, rd,
744 rn, rm, 0, LSL);
745 case 0x0:
746 return new Uadd8RegCc(machInst, rd,
747 rn, rm, 0, LSL);
748 case 0x4:
749 return new Usub8RegCc(machInst, rd,
750 rn, rm, 0, LSL);
751 }
752 break;
753 case 0x1:
754 switch (op1) {
755 case 0x1:
756 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
757 case 0x2:
758 return new UqasxReg(machInst, rd, rn, rm, 0, LSL);
759 case 0x6:
760 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL);
761 case 0x5:
762 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL);
763 case 0x0:
764 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
765 case 0x4:
766 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
767 }
768 break;
769 case 0x2:
770 switch (op1) {
771 case 0x1:
772 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL);
773 case 0x2:
774 return new UhasxReg(machInst, rd, rn, rm, 0, LSL);
775 case 0x6:
776 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL);
777 case 0x5:
778 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL);
779 case 0x0:
780 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL);
781 case 0x4:
782 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL);
783 }
784 break;
785 }
786 }
787 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) {
788 const uint32_t op1 = bits(machInst, 22, 20);
789 const uint32_t op2 = bits(machInst, 5, 4);
790 const IntRegIndex rd =
791 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
792 const IntRegIndex rm =
793 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
794 switch (op1) {
795 case 0x0:
796 switch (op2) {
797 case 0x0:
798 return new QaddRegCc(machInst, rd,
799 rm, rn, 0, LSL);
800 case 0x1:
801 return new QdaddRegCc(machInst, rd,
802 rm, rn, 0, LSL);
803 case 0x2:
804 return new QsubRegCc(machInst, rd,
805 rm, rn, 0, LSL);
806 case 0x3:
807 return new QdsubRegCc(machInst, rd,
808 rm, rn, 0, LSL);
809 }
810 break;
811 case 0x1:
812 switch (op2) {
813 case 0x0:
814 return new Rev(machInst, rd, rn);
815 case 0x1:
816 return new Rev16(machInst, rd, rn);
817 case 0x2:
818 return new Rbit(machInst, rd, rm);
819 case 0x3:
820 return new Revsh(machInst, rd, rn);
821 }
822 break;
823 case 0x2:
824 if (op2 == 0) {
825 return new Sel(machInst, rd, rn, rm);
826 }
827 break;
828 case 0x3:
829 if (op2 == 0) {
830 return new Clz(machInst, rd, rm);
831 }
832 break;
833 case 0x4:
834 switch (op2) {
835 case 0x0:
836 return new Crc32b(machInst, rd, rn, rm);
837 case 0x1:
838 return new Crc32h(machInst, rd, rn, rm);
839 case 0x2:
840 return new Crc32w(machInst, rd, rn, rm);
841 }
842 break;
843 case 0x5:
844 switch (op2) {
845 case 0x0:
846 return new Crc32cb(machInst, rd, rn, rm);
847 case 0x1:
848 return new Crc32ch(machInst, rd, rn, rm);
849 case 0x2:
850 return new Crc32cw(machInst, rd, rn, rm);
851 }
852 break;
853 }
854 }
855 return new Unknown(machInst);
856 }
857 }
858 '''
859}};
860
861def format Thumb16ShiftAddSubMoveCmp() {{
862 decode_block = '''
863 {
864 const uint32_t imm5 = bits(machInst, 10, 6);
865 const uint32_t imm3 = bits(machInst, 8, 6);
866 const uint32_t imm8 = bits(machInst, 7, 0);
867 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
868 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
869 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
870 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
871 switch (bits(machInst, 13, 11)) {
872 case 0x0: // lsl
873 if (machInst.itstateMask) {
874 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
875 } else {
876 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
877 }
878 case 0x1: // lsr
879 if (machInst.itstateMask) {
880 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
881 } else {
882 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
883 }
884 case 0x2: // asr
885 if (machInst.itstateMask) {
886 return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
887 } else {
888 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
889 }
890 case 0x3:
891 switch (bits(machInst, 10, 9)) {
892 case 0x0:
893 if (machInst.itstateMask) {
894 return new AddReg(machInst, rd, rn, rm, 0, LSL);
895 } else {
896 return new AddRegCc(machInst, rd, rn, rm, 0, LSL);
897 }
898 case 0x1:
899 if (machInst.itstateMask) {
900 return new SubReg(machInst, rd, rn, rm, 0, LSL);
901 } else {
902 return new SubRegCc(machInst, rd, rn, rm, 0, LSL);
903 }
904 case 0x2:
905 if (machInst.itstateMask) {
906 return new AddImm(machInst, rd, rn, imm3, true);
907 } else {
908 return new AddImmCc(machInst, rd, rn, imm3, true);
909 }
910 case 0x3:
911 if (machInst.itstateMask) {
912 return new SubImm(machInst, rd, rn, imm3, true);
913 } else {
914 return new SubImmCc(machInst, rd, rn, imm3, true);
915 }
|
| 916 default:
917 M5_UNREACHABLE;
|
919 }
920 case 0x4:
921 if (machInst.itstateMask) {
922 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false);
923 } else {
924 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
925 }
926 case 0x5:
927 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
928 case 0x6:
929 if (machInst.itstateMask) {
930 return new AddImm(machInst, rd8, rd8, imm8, true);
931 } else {
932 return new AddImmCc(machInst, rd8, rd8, imm8, true);
933 }
934 case 0x7:
935 if (machInst.itstateMask) {
936 return new SubImm(machInst, rd8, rd8, imm8, true);
937 } else {
938 return new SubImmCc(machInst, rd8, rd8, imm8, true);
939 }
| 918 }
919 case 0x4:
920 if (machInst.itstateMask) {
921 return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false);
922 } else {
923 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
924 }
925 case 0x5:
926 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
927 case 0x6:
928 if (machInst.itstateMask) {
929 return new AddImm(machInst, rd8, rd8, imm8, true);
930 } else {
931 return new AddImmCc(machInst, rd8, rd8, imm8, true);
932 }
933 case 0x7:
934 if (machInst.itstateMask) {
935 return new SubImm(machInst, rd8, rd8, imm8, true);
936 } else {
937 return new SubImmCc(machInst, rd8, rd8, imm8, true);
938 }
|
| 939 default:
940 M5_UNREACHABLE;
|
940 }
941 }
942 '''
943}};
944
945def format Thumb16DataProcessing() {{
946 decode_block = '''
947 {
948 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
949 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
950 switch (bits(machInst, 9, 6)) {
951 case 0x0:
952 if (machInst.itstateMask) {
953 return new AndReg(machInst, rdn, rdn, rm, 0, LSL);
954 } else {
955 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL);
956 }
957 case 0x1:
958 if (machInst.itstateMask) {
959 return new EorReg(machInst, rdn, rdn, rm, 0, LSL);
960 } else {
961 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL);
962 }
963 case 0x2: //lsl
964 if (machInst.itstateMask) {
965 return new MovRegReg(machInst, rdn,
966 INTREG_ZERO, rdn, rm, LSL);
967 } else {
968 return new MovRegRegCc(machInst, rdn,
969 INTREG_ZERO, rdn, rm, LSL);
970 }
971 case 0x3: //lsr
972 if (machInst.itstateMask) {
973 return new MovRegReg(machInst, rdn,
974 INTREG_ZERO, rdn, rm, LSR);
975 } else {
976 return new MovRegRegCc(machInst, rdn,
977 INTREG_ZERO, rdn, rm, LSR);
978 }
979 case 0x4: //asr
980 if (machInst.itstateMask) {
981 return new MovRegReg(machInst, rdn,
982 INTREG_ZERO, rdn, rm, ASR);
983 } else {
984 return new MovRegRegCc(machInst, rdn,
985 INTREG_ZERO, rdn, rm, ASR);
986 }
987 case 0x5:
988 if (machInst.itstateMask) {
989 return new AdcReg(machInst, rdn, rdn, rm, 0, LSL);
990 } else {
991 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL);
992 }
993 case 0x6:
994 if (machInst.itstateMask) {
995 return new SbcReg(machInst, rdn, rdn, rm, 0, LSL);
996 } else {
997 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL);
998 }
999 case 0x7: // ror
1000 if (machInst.itstateMask) {
1001 return new MovRegReg(machInst, rdn,
1002 INTREG_ZERO, rdn, rm, ROR);
1003 } else {
1004 return new MovRegRegCc(machInst, rdn,
1005 INTREG_ZERO, rdn, rm, ROR);
1006 }
1007 case 0x8:
1008 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
1009 case 0x9:
1010 if (machInst.itstateMask) {
1011 return new RsbImm(machInst, rdn, rm, 0, true);
1012 } else {
1013 return new RsbImmCc(machInst, rdn, rm, 0, true);
1014 }
1015 case 0xa:
1016 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
1017 case 0xb:
1018 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
1019 case 0xc:
1020 if (machInst.itstateMask) {
1021 return new OrrReg(machInst, rdn, rdn, rm, 0, LSL);
1022 } else {
1023 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL);
1024 }
1025 case 0xd:
1026 if (machInst.itstateMask) {
1027 return new Mul(machInst, rdn, rm, rdn);
1028 } else {
1029 return new MulCc(machInst, rdn, rm, rdn);
1030 }
1031 case 0xe:
1032 if (machInst.itstateMask) {
1033 return new BicReg(machInst, rdn, rdn, rm, 0, LSL);
1034 } else {
1035 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
1036 }
1037 case 0xf:
1038 if (machInst.itstateMask) {
1039 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1040 } else {
1041 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1042 }
| 941 }
942 }
943 '''
944}};
945
946def format Thumb16DataProcessing() {{
947 decode_block = '''
948 {
949 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
950 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
951 switch (bits(machInst, 9, 6)) {
952 case 0x0:
953 if (machInst.itstateMask) {
954 return new AndReg(machInst, rdn, rdn, rm, 0, LSL);
955 } else {
956 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL);
957 }
958 case 0x1:
959 if (machInst.itstateMask) {
960 return new EorReg(machInst, rdn, rdn, rm, 0, LSL);
961 } else {
962 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL);
963 }
964 case 0x2: //lsl
965 if (machInst.itstateMask) {
966 return new MovRegReg(machInst, rdn,
967 INTREG_ZERO, rdn, rm, LSL);
968 } else {
969 return new MovRegRegCc(machInst, rdn,
970 INTREG_ZERO, rdn, rm, LSL);
971 }
972 case 0x3: //lsr
973 if (machInst.itstateMask) {
974 return new MovRegReg(machInst, rdn,
975 INTREG_ZERO, rdn, rm, LSR);
976 } else {
977 return new MovRegRegCc(machInst, rdn,
978 INTREG_ZERO, rdn, rm, LSR);
979 }
980 case 0x4: //asr
981 if (machInst.itstateMask) {
982 return new MovRegReg(machInst, rdn,
983 INTREG_ZERO, rdn, rm, ASR);
984 } else {
985 return new MovRegRegCc(machInst, rdn,
986 INTREG_ZERO, rdn, rm, ASR);
987 }
988 case 0x5:
989 if (machInst.itstateMask) {
990 return new AdcReg(machInst, rdn, rdn, rm, 0, LSL);
991 } else {
992 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL);
993 }
994 case 0x6:
995 if (machInst.itstateMask) {
996 return new SbcReg(machInst, rdn, rdn, rm, 0, LSL);
997 } else {
998 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL);
999 }
1000 case 0x7: // ror
1001 if (machInst.itstateMask) {
1002 return new MovRegReg(machInst, rdn,
1003 INTREG_ZERO, rdn, rm, ROR);
1004 } else {
1005 return new MovRegRegCc(machInst, rdn,
1006 INTREG_ZERO, rdn, rm, ROR);
1007 }
1008 case 0x8:
1009 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
1010 case 0x9:
1011 if (machInst.itstateMask) {
1012 return new RsbImm(machInst, rdn, rm, 0, true);
1013 } else {
1014 return new RsbImmCc(machInst, rdn, rm, 0, true);
1015 }
1016 case 0xa:
1017 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
1018 case 0xb:
1019 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
1020 case 0xc:
1021 if (machInst.itstateMask) {
1022 return new OrrReg(machInst, rdn, rdn, rm, 0, LSL);
1023 } else {
1024 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL);
1025 }
1026 case 0xd:
1027 if (machInst.itstateMask) {
1028 return new Mul(machInst, rdn, rm, rdn);
1029 } else {
1030 return new MulCc(machInst, rdn, rm, rdn);
1031 }
1032 case 0xe:
1033 if (machInst.itstateMask) {
1034 return new BicReg(machInst, rdn, rdn, rm, 0, LSL);
1035 } else {
1036 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
1037 }
1038 case 0xf:
1039 if (machInst.itstateMask) {
1040 return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1041 } else {
1042 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1043 }
|
| 1044 default:
1045 M5_UNREACHABLE;
|
1043 }
1044 }
1045 '''
1046}};
1047
1048def format Thumb16SpecDataAndBx() {{
1049 decode_block = '''
1050 {
1051 const IntRegIndex rdn =
1052 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
1053 (bits(machInst, 7) << 3));
1054 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
1055 switch (bits(machInst, 9, 8)) {
1056 case 0x0:
1057 return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
1058 case 0x1:
1059 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
1060 case 0x2:
1061 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1062 case 0x3:
1063 if (bits(machInst, 7) == 0) {
1064 return new BxReg(machInst,
1065 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
1066 COND_UC);
1067 } else {
1068 return new BlxReg(machInst,
1069 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
1070 COND_UC);
1071 }
| 1046 }
1047 }
1048 '''
1049}};
1050
1051def format Thumb16SpecDataAndBx() {{
1052 decode_block = '''
1053 {
1054 const IntRegIndex rdn =
1055 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
1056 (bits(machInst, 7) << 3));
1057 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
1058 switch (bits(machInst, 9, 8)) {
1059 case 0x0:
1060 return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
1061 case 0x1:
1062 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
1063 case 0x2:
1064 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
1065 case 0x3:
1066 if (bits(machInst, 7) == 0) {
1067 return new BxReg(machInst,
1068 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
1069 COND_UC);
1070 } else {
1071 return new BlxReg(machInst,
1072 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
1073 COND_UC);
1074 }
|
| 1075 default:
1076 M5_UNREACHABLE;
|
1072 }
1073 }
1074 '''
1075}};
1076
1077def format Thumb16Adr() {{
1078 decode_block = '''
1079 {
1080 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
1081 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
1082 return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false);
1083 }
1084 '''
1085}};
1086
1087def format Thumb16AddSp() {{
1088 decode_block = '''
1089 {
1090 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
1091 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
1092 return new AddImm(machInst, rd, INTREG_SP, imm8, true);
1093 }
1094 '''
1095}};
1096
1097def format ArmMisc() {{
1098 decode_block = '''
1099 {
1100 const uint32_t unrotated = bits(machInst, 7, 0);
1101 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
1102 const uint32_t imm = rotate_imm(unrotated, rotation);
1103 const uint8_t byteMask = bits(machInst, 19, 16);
1104 switch (OPCODE) {
1105 case 0x8:
1106 return new MovImm(machInst, (IntRegIndex)(uint32_t)RD,
1107 (IntRegIndex)INTREG_ZERO,
1108 bits(machInst, 11, 0) | (bits(machInst, 19, 16) << 12),
1109 false);
1110 case 0x9:
1111 if (RN == 0) {
1112 switch (IMM) {
1113 case 0x0:
1114 return new NopInst(machInst);
1115 case 0x1:
1116 return new YieldInst(machInst);
1117 case 0x2:
1118 return new WfeInst(machInst);
1119 case 0x3:
1120 return new WfiInst(machInst);
1121 case 0x4:
1122 return new SevInst(machInst);
1123 default:
1124 return new Unknown(machInst);
1125 }
1126 } else {
1127 return new MsrCpsrImm(machInst, imm, byteMask);
1128 }
1129 case 0xa:
1130 {
1131 const uint32_t timm = (bits(machInst, 19, 16) << 12) |
1132 bits(machInst, 11, 0);
1133 return new MovtImm(machInst, (IntRegIndex)(uint32_t)RD,
1134 (IntRegIndex)(uint32_t)RD, timm, true);
1135 }
1136 case 0xb:
1137 return new MsrSpsrImm(machInst, imm, byteMask);
1138 default:
1139 return new Unknown(machInst);
1140 }
1141 }
1142 '''
1143}};
1144
1145def format Thumb16Misc() {{
1146 decode_block = '''
1147 {
1148 switch (bits(machInst, 11, 8)) {
1149 case 0x0:
1150 if (bits(machInst, 7)) {
1151 return new SubImm(machInst, INTREG_SP, INTREG_SP,
1152 bits(machInst, 6, 0) << 2, true);
1153 } else {
1154 return new AddImm(machInst, INTREG_SP, INTREG_SP,
1155 bits(machInst, 6, 0) << 2, true);
1156 }
1157 case 0x2:
1158 {
1159 const IntRegIndex rd =
1160 (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
1161 const IntRegIndex rm =
1162 (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
1163 switch (bits(machInst, 7, 6)) {
1164 case 0x0:
1165 return new Sxth(machInst, rd, 0, rm);
1166 case 0x1:
1167 return new Sxtb(machInst, rd, 0, rm);
1168 case 0x2:
1169 return new Uxth(machInst, rd, 0, rm);
1170 case 0x3:
1171 return new Uxtb(machInst, rd, 0, rm);
| 1077 }
1078 }
1079 '''
1080}};
1081
1082def format Thumb16Adr() {{
1083 decode_block = '''
1084 {
1085 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
1086 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
1087 return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false);
1088 }
1089 '''
1090}};
1091
1092def format Thumb16AddSp() {{
1093 decode_block = '''
1094 {
1095 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
1096 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
1097 return new AddImm(machInst, rd, INTREG_SP, imm8, true);
1098 }
1099 '''
1100}};
1101
1102def format ArmMisc() {{
1103 decode_block = '''
1104 {
1105 const uint32_t unrotated = bits(machInst, 7, 0);
1106 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
1107 const uint32_t imm = rotate_imm(unrotated, rotation);
1108 const uint8_t byteMask = bits(machInst, 19, 16);
1109 switch (OPCODE) {
1110 case 0x8:
1111 return new MovImm(machInst, (IntRegIndex)(uint32_t)RD,
1112 (IntRegIndex)INTREG_ZERO,
1113 bits(machInst, 11, 0) | (bits(machInst, 19, 16) << 12),
1114 false);
1115 case 0x9:
1116 if (RN == 0) {
1117 switch (IMM) {
1118 case 0x0:
1119 return new NopInst(machInst);
1120 case 0x1:
1121 return new YieldInst(machInst);
1122 case 0x2:
1123 return new WfeInst(machInst);
1124 case 0x3:
1125 return new WfiInst(machInst);
1126 case 0x4:
1127 return new SevInst(machInst);
1128 default:
1129 return new Unknown(machInst);
1130 }
1131 } else {
1132 return new MsrCpsrImm(machInst, imm, byteMask);
1133 }
1134 case 0xa:
1135 {
1136 const uint32_t timm = (bits(machInst, 19, 16) << 12) |
1137 bits(machInst, 11, 0);
1138 return new MovtImm(machInst, (IntRegIndex)(uint32_t)RD,
1139 (IntRegIndex)(uint32_t)RD, timm, true);
1140 }
1141 case 0xb:
1142 return new MsrSpsrImm(machInst, imm, byteMask);
1143 default:
1144 return new Unknown(machInst);
1145 }
1146 }
1147 '''
1148}};
1149
1150def format Thumb16Misc() {{
1151 decode_block = '''
1152 {
1153 switch (bits(machInst, 11, 8)) {
1154 case 0x0:
1155 if (bits(machInst, 7)) {
1156 return new SubImm(machInst, INTREG_SP, INTREG_SP,
1157 bits(machInst, 6, 0) << 2, true);
1158 } else {
1159 return new AddImm(machInst, INTREG_SP, INTREG_SP,
1160 bits(machInst, 6, 0) << 2, true);
1161 }
1162 case 0x2:
1163 {
1164 const IntRegIndex rd =
1165 (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
1166 const IntRegIndex rm =
1167 (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
1168 switch (bits(machInst, 7, 6)) {
1169 case 0x0:
1170 return new Sxth(machInst, rd, 0, rm);
1171 case 0x1:
1172 return new Sxtb(machInst, rd, 0, rm);
1173 case 0x2:
1174 return new Uxth(machInst, rd, 0, rm);
1175 case 0x3:
1176 return new Uxtb(machInst, rd, 0, rm);
|
| 1177 default:
1178 M5_UNREACHABLE;
|
1172 }
1173 }
1174 case 0x1:
1175 case 0x3:
1176 return new Cbz(machInst,
1177 (bits(machInst, 9) << 6) |
1178 (bits(machInst, 7, 3) << 1),
1179 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
1180 case 0x4:
1181 case 0x5:
1182 {
1183 const uint32_t m = bits(machInst, 8);
1184 const uint32_t regList = bits(machInst, 7, 0) | (m << 14);
1185 return new LdmStm(machInst, INTREG_SP, false, false, false,
1186 true, false, regList);
1187 }
1188 case 0x6:
1189 {
1190 const uint32_t opBits = bits(machInst, 7, 5);
1191 if (opBits == 2) {
1192 return new Setend(machInst, bits(machInst, 3));
1193 } else if (opBits == 3) {
1194 const bool enable = (bits(machInst, 4) == 0);
1195 const uint32_t mods = (bits(machInst, 2, 0) << 5) |
1196 ((enable ? 1 : 0) << 9);
1197 return new Cps(machInst, mods);
1198 }
| 1179 }
1180 }
1181 case 0x1:
1182 case 0x3:
1183 return new Cbz(machInst,
1184 (bits(machInst, 9) << 6) |
1185 (bits(machInst, 7, 3) << 1),
1186 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
1187 case 0x4:
1188 case 0x5:
1189 {
1190 const uint32_t m = bits(machInst, 8);
1191 const uint32_t regList = bits(machInst, 7, 0) | (m << 14);
1192 return new LdmStm(machInst, INTREG_SP, false, false, false,
1193 true, false, regList);
1194 }
1195 case 0x6:
1196 {
1197 const uint32_t opBits = bits(machInst, 7, 5);
1198 if (opBits == 2) {
1199 return new Setend(machInst, bits(machInst, 3));
1200 } else if (opBits == 3) {
1201 const bool enable = (bits(machInst, 4) == 0);
1202 const uint32_t mods = (bits(machInst, 2, 0) << 5) |
1203 ((enable ? 1 : 0) << 9);
1204 return new Cps(machInst, mods);
1205 }
|
| 1206 return new Unknown(machInst);
|
1199 }
1200 case 0xa:
1201 {
1202 const uint8_t op1 = bits(machInst, 7, 6);
1203 if (op1 == 0x2) {
1204 return new Hlt(machInst, bits(machInst, 5, 0));
1205 } else {
1206 IntRegIndex rd =
1207 (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
1208 IntRegIndex rm =
1209 (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
1210
1211 switch (op1) {
1212 case 0x0:
1213 return new Rev(machInst, rd, rm);
1214 case 0x1:
1215 return new Rev16(machInst, rd, rm);
1216 case 0x3:
1217 return new Revsh(machInst, rd, rm);
1218 default:
1219 break;
1220 }
1221 }
1222 }
1223 break;
1224 case 0x9:
1225 case 0xb:
1226 return new Cbnz(machInst,
1227 (bits(machInst, 9) << 6) |
1228 (bits(machInst, 7, 3) << 1),
1229 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
1230 case 0xc:
1231 case 0xd:
1232 {
1233 const uint32_t p = bits(machInst, 8);
1234 const uint32_t regList = bits(machInst, 7, 0) | (p << 15);
1235 return new LdmStm(machInst, INTREG_SP, true, true, false,
1236 true, true, regList);
1237 }
1238 case 0xe:
1239 return new BkptInst(machInst);
1240 case 0xf:
1241 if (bits(machInst, 3, 0) != 0)
1242 return new ItInst(machInst);
1243 switch (bits(machInst, 7, 4)) {
1244 case 0x0:
1245 return new NopInst(machInst);
1246 case 0x1:
1247 return new YieldInst(machInst);
1248 case 0x2:
1249 return new WfeInst(machInst);
1250 case 0x3:
1251 return new WfiInst(machInst);
1252 case 0x4:
1253 return new SevInst(machInst);
1254 default:
1255 return new WarnUnimplemented("unallocated_hint", machInst);
1256 }
1257 default:
1258 break;
1259 }
1260 return new Unknown(machInst);
1261 }
1262 '''
1263}};
1264
1265def format Thumb32DataProcModImm() {{
1266
1267 def decInst(mnem, dest="rd", op1="rn"):
1268 return '''
1269 if (s) {
1270 return new %(mnem)sImmCc(machInst, %(dest)s,
1271 %(op1)s, imm, rotC);
1272 } else {
1273 return new %(mnem)sImm(machInst, %(dest)s,
1274 %(op1)s, imm, rotC);
1275 }
1276 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
1277
1278 decode_block = '''
1279 {
1280 const uint32_t op = bits(machInst, 24, 21);
1281 const bool s = (bits(machInst, 20) == 1);
1282 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
1283 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
1284 const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
1285 bits(machInst, 14, 12);
1286 const bool rotC = ctrlImm > 3;
1287 const uint32_t dataImm = bits(machInst, 7, 0);
1288 const uint32_t imm = modified_imm(ctrlImm, dataImm);
1289 switch (op) {
1290 case 0x0:
1291 if (rd == INTREG_PC) {
1292 %(tst)s
1293 } else {
1294 %(and)s
1295 }
1296 case 0x1:
1297 %(bic)s
1298 case 0x2:
1299 if (rn == INTREG_PC) {
1300 %(mov)s
1301 } else {
1302 %(orr)s
1303 }
1304 case 0x3:
1305 if (rn == INTREG_PC) {
1306 %(mvn)s
1307 } else {
1308 %(orn)s
1309 }
1310 case 0x4:
1311 if (rd == INTREG_PC) {
1312 %(teq)s
1313 } else {
1314 %(eor)s
1315 }
1316 case 0x8:
1317 if (rd == INTREG_PC) {
1318 %(cmn)s
1319 } else {
1320 %(add)s
1321 }
1322 case 0xa:
1323 %(adc)s
1324 case 0xb:
1325 %(sbc)s
1326 case 0xd:
1327 if (rd == INTREG_PC) {
1328 %(cmp)s
1329 } else {
1330 %(sub)s
1331 }
1332 case 0xe:
1333 %(rsb)s
1334 default:
1335 return new Unknown(machInst);
1336 }
1337 }
1338 ''' % {
1339 "tst" : decInst("Tst", "INTREG_ZERO"),
1340 "and" : decInst("And"),
1341 "bic" : decInst("Bic"),
1342 "mov" : decInst("Mov", op1="INTREG_ZERO"),
1343 "orr" : decInst("Orr"),
1344 "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
1345 "orn" : decInst("Orn"),
1346 "teq" : decInst("Teq", dest="INTREG_ZERO"),
1347 "eor" : decInst("Eor"),
1348 "cmn" : decInst("Cmn", dest="INTREG_ZERO"),
1349 "add" : decInst("Add"),
1350 "adc" : decInst("Adc"),
1351 "sbc" : decInst("Sbc"),
1352 "cmp" : decInst("Cmp", dest="INTREG_ZERO"),
1353 "sub" : decInst("Sub"),
1354 "rsb" : decInst("Rsb")
1355 }
1356}};
1357
1358def format Thumb32DataProcPlainBin() {{
1359 decode_block = '''
1360 {
1361 const uint32_t op = bits(machInst, 24, 20);
1362 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
1363 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
1364 switch (op) {
1365 case 0x0:
1366 {
1367 const uint32_t imm = bits(machInst, 7, 0) |
1368 (bits(machInst, 14, 12) << 8) |
1369 (bits(machInst, 26) << 11);
1370 if (rn == 0xf) {
1371 return new AdrImm(machInst, rd, (IntRegIndex)1,
1372 imm, false);
1373 } else {
1374 return new AddImm(machInst, rd, rn, imm, true);
1375 }
1376 }
1377 case 0x4:
1378 {
1379 const uint32_t imm = bits(machInst, 7, 0) |
1380 (bits(machInst, 14, 12) << 8) |
1381 (bits(machInst, 26) << 11) |
1382 (bits(machInst, 19, 16) << 12);
1383 return new MovImm(machInst, rd, INTREG_ZERO, imm, true);
1384 }
1385 case 0xa:
1386 {
1387 const uint32_t imm = bits(machInst, 7, 0) |
1388 (bits(machInst, 14, 12) << 8) |
1389 (bits(machInst, 26) << 11);
1390 if (rn == 0xf) {
1391 return new AdrImm(machInst, rd, (IntRegIndex)0,
1392 imm, false);
1393 } else {
1394 return new SubImm(machInst, rd, rn, imm, true);
1395 }
1396 }
1397 case 0xc:
1398 {
1399 const uint32_t imm = bits(machInst, 7, 0) |
1400 (bits(machInst, 14, 12) << 8) |
1401 (bits(machInst, 26) << 11) |
1402 (bits(machInst, 19, 16) << 12);
1403 return new MovtImm(machInst, rd, rd, imm, true);
1404 }
1405 case 0x12:
1406 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1407 const uint32_t satImm = bits(machInst, 4, 0);
1408 return new Ssat16(machInst, rd, satImm + 1, rn);
1409 }
| 1207 }
1208 case 0xa:
1209 {
1210 const uint8_t op1 = bits(machInst, 7, 6);
1211 if (op1 == 0x2) {
1212 return new Hlt(machInst, bits(machInst, 5, 0));
1213 } else {
1214 IntRegIndex rd =
1215 (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
1216 IntRegIndex rm =
1217 (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
1218
1219 switch (op1) {
1220 case 0x0:
1221 return new Rev(machInst, rd, rm);
1222 case 0x1:
1223 return new Rev16(machInst, rd, rm);
1224 case 0x3:
1225 return new Revsh(machInst, rd, rm);
1226 default:
1227 break;
1228 }
1229 }
1230 }
1231 break;
1232 case 0x9:
1233 case 0xb:
1234 return new Cbnz(machInst,
1235 (bits(machInst, 9) << 6) |
1236 (bits(machInst, 7, 3) << 1),
1237 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
1238 case 0xc:
1239 case 0xd:
1240 {
1241 const uint32_t p = bits(machInst, 8);
1242 const uint32_t regList = bits(machInst, 7, 0) | (p << 15);
1243 return new LdmStm(machInst, INTREG_SP, true, true, false,
1244 true, true, regList);
1245 }
1246 case 0xe:
1247 return new BkptInst(machInst);
1248 case 0xf:
1249 if (bits(machInst, 3, 0) != 0)
1250 return new ItInst(machInst);
1251 switch (bits(machInst, 7, 4)) {
1252 case 0x0:
1253 return new NopInst(machInst);
1254 case 0x1:
1255 return new YieldInst(machInst);
1256 case 0x2:
1257 return new WfeInst(machInst);
1258 case 0x3:
1259 return new WfiInst(machInst);
1260 case 0x4:
1261 return new SevInst(machInst);
1262 default:
1263 return new WarnUnimplemented("unallocated_hint", machInst);
1264 }
1265 default:
1266 break;
1267 }
1268 return new Unknown(machInst);
1269 }
1270 '''
1271}};
1272
1273def format Thumb32DataProcModImm() {{
1274
1275 def decInst(mnem, dest="rd", op1="rn"):
1276 return '''
1277 if (s) {
1278 return new %(mnem)sImmCc(machInst, %(dest)s,
1279 %(op1)s, imm, rotC);
1280 } else {
1281 return new %(mnem)sImm(machInst, %(dest)s,
1282 %(op1)s, imm, rotC);
1283 }
1284 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
1285
1286 decode_block = '''
1287 {
1288 const uint32_t op = bits(machInst, 24, 21);
1289 const bool s = (bits(machInst, 20) == 1);
1290 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
1291 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
1292 const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
1293 bits(machInst, 14, 12);
1294 const bool rotC = ctrlImm > 3;
1295 const uint32_t dataImm = bits(machInst, 7, 0);
1296 const uint32_t imm = modified_imm(ctrlImm, dataImm);
1297 switch (op) {
1298 case 0x0:
1299 if (rd == INTREG_PC) {
1300 %(tst)s
1301 } else {
1302 %(and)s
1303 }
1304 case 0x1:
1305 %(bic)s
1306 case 0x2:
1307 if (rn == INTREG_PC) {
1308 %(mov)s
1309 } else {
1310 %(orr)s
1311 }
1312 case 0x3:
1313 if (rn == INTREG_PC) {
1314 %(mvn)s
1315 } else {
1316 %(orn)s
1317 }
1318 case 0x4:
1319 if (rd == INTREG_PC) {
1320 %(teq)s
1321 } else {
1322 %(eor)s
1323 }
1324 case 0x8:
1325 if (rd == INTREG_PC) {
1326 %(cmn)s
1327 } else {
1328 %(add)s
1329 }
1330 case 0xa:
1331 %(adc)s
1332 case 0xb:
1333 %(sbc)s
1334 case 0xd:
1335 if (rd == INTREG_PC) {
1336 %(cmp)s
1337 } else {
1338 %(sub)s
1339 }
1340 case 0xe:
1341 %(rsb)s
1342 default:
1343 return new Unknown(machInst);
1344 }
1345 }
1346 ''' % {
1347 "tst" : decInst("Tst", "INTREG_ZERO"),
1348 "and" : decInst("And"),
1349 "bic" : decInst("Bic"),
1350 "mov" : decInst("Mov", op1="INTREG_ZERO"),
1351 "orr" : decInst("Orr"),
1352 "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
1353 "orn" : decInst("Orn"),
1354 "teq" : decInst("Teq", dest="INTREG_ZERO"),
1355 "eor" : decInst("Eor"),
1356 "cmn" : decInst("Cmn", dest="INTREG_ZERO"),
1357 "add" : decInst("Add"),
1358 "adc" : decInst("Adc"),
1359 "sbc" : decInst("Sbc"),
1360 "cmp" : decInst("Cmp", dest="INTREG_ZERO"),
1361 "sub" : decInst("Sub"),
1362 "rsb" : decInst("Rsb")
1363 }
1364}};
1365
1366def format Thumb32DataProcPlainBin() {{
1367 decode_block = '''
1368 {
1369 const uint32_t op = bits(machInst, 24, 20);
1370 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
1371 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
1372 switch (op) {
1373 case 0x0:
1374 {
1375 const uint32_t imm = bits(machInst, 7, 0) |
1376 (bits(machInst, 14, 12) << 8) |
1377 (bits(machInst, 26) << 11);
1378 if (rn == 0xf) {
1379 return new AdrImm(machInst, rd, (IntRegIndex)1,
1380 imm, false);
1381 } else {
1382 return new AddImm(machInst, rd, rn, imm, true);
1383 }
1384 }
1385 case 0x4:
1386 {
1387 const uint32_t imm = bits(machInst, 7, 0) |
1388 (bits(machInst, 14, 12) << 8) |
1389 (bits(machInst, 26) << 11) |
1390 (bits(machInst, 19, 16) << 12);
1391 return new MovImm(machInst, rd, INTREG_ZERO, imm, true);
1392 }
1393 case 0xa:
1394 {
1395 const uint32_t imm = bits(machInst, 7, 0) |
1396 (bits(machInst, 14, 12) << 8) |
1397 (bits(machInst, 26) << 11);
1398 if (rn == 0xf) {
1399 return new AdrImm(machInst, rd, (IntRegIndex)0,
1400 imm, false);
1401 } else {
1402 return new SubImm(machInst, rd, rn, imm, true);
1403 }
1404 }
1405 case 0xc:
1406 {
1407 const uint32_t imm = bits(machInst, 7, 0) |
1408 (bits(machInst, 14, 12) << 8) |
1409 (bits(machInst, 26) << 11) |
1410 (bits(machInst, 19, 16) << 12);
1411 return new MovtImm(machInst, rd, rd, imm, true);
1412 }
1413 case 0x12:
1414 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1415 const uint32_t satImm = bits(machInst, 4, 0);
1416 return new Ssat16(machInst, rd, satImm + 1, rn);
1417 }
|
1410 // Fall through on purpose...
| 1418 M5_FALLTHROUGH;
|
1411 case 0x10:
1412 {
1413 const uint32_t satImm = bits(machInst, 4, 0);
1414 const uint32_t imm = bits(machInst, 7, 6) |
1415 (bits(machInst, 14, 12) << 2);
1416 const ArmShiftType type =
1417 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1418 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
1419 }
1420 case 0x14:
1421 {
1422 const uint32_t lsb = bits(machInst, 7, 6) |
1423 (bits(machInst, 14, 12) << 2);
1424 const uint32_t msb = lsb + bits(machInst, 4, 0);
1425 return new Sbfx(machInst, rd, rn, lsb, msb);
1426 }
1427 case 0x16:
1428 {
1429 const uint32_t lsb = bits(machInst, 7, 6) |
1430 (bits(machInst, 14, 12) << 2);
1431 const uint32_t msb = bits(machInst, 4, 0);
1432 if (rn == 0xf) {
1433 return new Bfc(machInst, rd, rd, lsb, msb);
1434 } else {
1435 return new Bfi(machInst, rd, rn, lsb, msb);
1436 }
1437 }
1438 case 0x1a:
1439 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1440 const uint32_t satImm = bits(machInst, 4, 0);
1441 return new Usat16(machInst, rd, satImm, rn);
1442 }
| 1419 case 0x10:
1420 {
1421 const uint32_t satImm = bits(machInst, 4, 0);
1422 const uint32_t imm = bits(machInst, 7, 6) |
1423 (bits(machInst, 14, 12) << 2);
1424 const ArmShiftType type =
1425 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1426 return new Ssat(machInst, rd, satImm + 1, rn, imm, type);
1427 }
1428 case 0x14:
1429 {
1430 const uint32_t lsb = bits(machInst, 7, 6) |
1431 (bits(machInst, 14, 12) << 2);
1432 const uint32_t msb = lsb + bits(machInst, 4, 0);
1433 return new Sbfx(machInst, rd, rn, lsb, msb);
1434 }
1435 case 0x16:
1436 {
1437 const uint32_t lsb = bits(machInst, 7, 6) |
1438 (bits(machInst, 14, 12) << 2);
1439 const uint32_t msb = bits(machInst, 4, 0);
1440 if (rn == 0xf) {
1441 return new Bfc(machInst, rd, rd, lsb, msb);
1442 } else {
1443 return new Bfi(machInst, rd, rn, lsb, msb);
1444 }
1445 }
1446 case 0x1a:
1447 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
1448 const uint32_t satImm = bits(machInst, 4, 0);
1449 return new Usat16(machInst, rd, satImm, rn);
1450 }
|
1443 // Fall through on purpose...
| 1451 M5_FALLTHROUGH;
|
1444 case 0x18:
1445 {
1446 const uint32_t satImm = bits(machInst, 4, 0);
1447 const uint32_t imm = bits(machInst, 7, 6) |
1448 (bits(machInst, 14, 12) << 2);
1449 const ArmShiftType type =
1450 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1451 return new Usat(machInst, rd, satImm, rn, imm, type);
1452 }
1453 case 0x1c:
1454 {
1455 const uint32_t lsb = bits(machInst, 7, 6) |
1456 (bits(machInst, 14, 12) << 2);
1457 const uint32_t msb = lsb + bits(machInst, 4, 0);
1458 return new Ubfx(machInst, rd, rn, lsb, msb);
1459 }
1460 default:
1461 return new Unknown(machInst);
1462 }
1463 }
1464 '''
1465}};
1466
1467def format Thumb32DataProcShiftReg() {{
1468
1469 def decInst(mnem, dest="rd", op1="rn"):
1470 return '''
1471 if (s) {
1472 return new %(mnem)sRegCc(machInst, %(dest)s,
1473 %(op1)s, rm, amt, type);
1474 } else {
1475 return new %(mnem)sReg(machInst, %(dest)s,
1476 %(op1)s, rm, amt, type);
1477 }
1478 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
1479
1480 decode_block = '''
1481 {
1482 const uint32_t op = bits(machInst, 24, 21);
1483 const bool s = (bits(machInst, 20) == 1);
1484 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
1485 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
1486 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
1487 const uint32_t amt = (bits(machInst, 14, 12) << 2) |
1488 bits(machInst, 7, 6);
1489 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4);
1490 switch (op) {
1491 case 0x0:
1492 if (rd == INTREG_PC) {
1493 %(tst)s
1494 } else {
1495 %(and)s
1496 }
1497 case 0x1:
1498 %(bic)s
1499 case 0x2:
1500 if (rn == INTREG_PC) {
1501 %(mov)s
1502 } else {
1503 %(orr)s
1504 }
1505 case 0x3:
1506 if (rn == INTREG_PC) {
1507 %(mvn)s
1508 } else {
1509 %(orn)s
1510 }
1511 case 0x4:
1512 if (rd == INTREG_PC) {
1513 %(teq)s
1514 } else {
1515 %(eor)s
1516 }
1517 case 0x6:
1518 if (type) {
1519 return new PkhtbReg(machInst, rd, rn, rm, amt, type);
1520 } else {
1521 return new PkhbtReg(machInst, rd, rn, rm, amt, type);
1522 }
1523 case 0x8:
1524 if (rd == INTREG_PC) {
1525 %(cmn)s
1526 } else {
1527 %(add)s
1528 }
1529 case 0xa:
1530 %(adc)s
1531 case 0xb:
1532 %(sbc)s
1533 case 0xd:
1534 if (rd == INTREG_PC) {
1535 %(cmp)s
1536 } else {
1537 %(sub)s
1538 }
1539 case 0xe:
1540 %(rsb)s
1541 default:
1542 return new Unknown(machInst);
1543 }
1544 }
1545 ''' % {
1546 "tst" : decInst("Tst", "INTREG_ZERO"),
1547 "and" : decInst("And"),
1548 "bic" : decInst("Bic"),
1549 "mov" : decInst("Mov", op1="INTREG_ZERO"),
1550 "orr" : decInst("Orr"),
1551 "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
1552 "orn" : decInst("Orn"),
1553 "teq" : decInst("Teq", "INTREG_ZERO"),
1554 "eor" : decInst("Eor"),
1555 "cmn" : decInst("Cmn", "INTREG_ZERO"),
1556 "add" : decInst("Add"),
1557 "adc" : decInst("Adc"),
1558 "sbc" : decInst("Sbc"),
1559 "cmp" : decInst("Cmp", "INTREG_ZERO"),
1560 "sub" : decInst("Sub"),
1561 "rsb" : decInst("Rsb")
1562 }
1563}};
| 1452 case 0x18:
1453 {
1454 const uint32_t satImm = bits(machInst, 4, 0);
1455 const uint32_t imm = bits(machInst, 7, 6) |
1456 (bits(machInst, 14, 12) << 2);
1457 const ArmShiftType type =
1458 (ArmShiftType)(uint32_t)bits(machInst, 21, 20);
1459 return new Usat(machInst, rd, satImm, rn, imm, type);
1460 }
1461 case 0x1c:
1462 {
1463 const uint32_t lsb = bits(machInst, 7, 6) |
1464 (bits(machInst, 14, 12) << 2);
1465 const uint32_t msb = lsb + bits(machInst, 4, 0);
1466 return new Ubfx(machInst, rd, rn, lsb, msb);
1467 }
1468 default:
1469 return new Unknown(machInst);
1470 }
1471 }
1472 '''
1473}};
1474
1475def format Thumb32DataProcShiftReg() {{
1476
1477 def decInst(mnem, dest="rd", op1="rn"):
1478 return '''
1479 if (s) {
1480 return new %(mnem)sRegCc(machInst, %(dest)s,
1481 %(op1)s, rm, amt, type);
1482 } else {
1483 return new %(mnem)sReg(machInst, %(dest)s,
1484 %(op1)s, rm, amt, type);
1485 }
1486 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
1487
1488 decode_block = '''
1489 {
1490 const uint32_t op = bits(machInst, 24, 21);
1491 const bool s = (bits(machInst, 20) == 1);
1492 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
1493 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
1494 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
1495 const uint32_t amt = (bits(machInst, 14, 12) << 2) |
1496 bits(machInst, 7, 6);
1497 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4);
1498 switch (op) {
1499 case 0x0:
1500 if (rd == INTREG_PC) {
1501 %(tst)s
1502 } else {
1503 %(and)s
1504 }
1505 case 0x1:
1506 %(bic)s
1507 case 0x2:
1508 if (rn == INTREG_PC) {
1509 %(mov)s
1510 } else {
1511 %(orr)s
1512 }
1513 case 0x3:
1514 if (rn == INTREG_PC) {
1515 %(mvn)s
1516 } else {
1517 %(orn)s
1518 }
1519 case 0x4:
1520 if (rd == INTREG_PC) {
1521 %(teq)s
1522 } else {
1523 %(eor)s
1524 }
1525 case 0x6:
1526 if (type) {
1527 return new PkhtbReg(machInst, rd, rn, rm, amt, type);
1528 } else {
1529 return new PkhbtReg(machInst, rd, rn, rm, amt, type);
1530 }
1531 case 0x8:
1532 if (rd == INTREG_PC) {
1533 %(cmn)s
1534 } else {
1535 %(add)s
1536 }
1537 case 0xa:
1538 %(adc)s
1539 case 0xb:
1540 %(sbc)s
1541 case 0xd:
1542 if (rd == INTREG_PC) {
1543 %(cmp)s
1544 } else {
1545 %(sub)s
1546 }
1547 case 0xe:
1548 %(rsb)s
1549 default:
1550 return new Unknown(machInst);
1551 }
1552 }
1553 ''' % {
1554 "tst" : decInst("Tst", "INTREG_ZERO"),
1555 "and" : decInst("And"),
1556 "bic" : decInst("Bic"),
1557 "mov" : decInst("Mov", op1="INTREG_ZERO"),
1558 "orr" : decInst("Orr"),
1559 "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
1560 "orn" : decInst("Orn"),
1561 "teq" : decInst("Teq", "INTREG_ZERO"),
1562 "eor" : decInst("Eor"),
1563 "cmn" : decInst("Cmn", "INTREG_ZERO"),
1564 "add" : decInst("Add"),
1565 "adc" : decInst("Adc"),
1566 "sbc" : decInst("Sbc"),
1567 "cmp" : decInst("Cmp", "INTREG_ZERO"),
1568 "sub" : decInst("Sub"),
1569 "rsb" : decInst("Rsb")
1570 }
1571}};
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