data.isa (7419:10e7f0f18461) | data.isa (7432:7501a6d33e3e) |
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1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 1121 unchanged lines hidden (view full) --- 1130 case 0x0: 1131 if (bits(machInst, 7)) { 1132 return new SubImm(machInst, INTREG_SP, INTREG_SP, 1133 bits(machInst, 6, 0) << 2, true); 1134 } else { 1135 return new AddImm(machInst, INTREG_SP, INTREG_SP, 1136 bits(machInst, 6, 0) << 2, true); 1137 } | 1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 1121 unchanged lines hidden (view full) --- 1130 case 0x0: 1131 if (bits(machInst, 7)) { 1132 return new SubImm(machInst, INTREG_SP, INTREG_SP, 1133 bits(machInst, 6, 0) << 2, true); 1134 } else { 1135 return new AddImm(machInst, INTREG_SP, INTREG_SP, 1136 bits(machInst, 6, 0) << 2, true); 1137 } |
1138 case 0x1: 1139 return new Cbz(machInst, 1140 (bits(machInst, 9) << 6) | 1141 (bits(machInst, 7, 3) << 1), 1142 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); | |
1143 case 0x2: 1144 { 1145 const IntRegIndex rd = 1146 (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 1147 const IntRegIndex rm = 1148 (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 1149 switch (bits(machInst, 7, 6)) { 1150 case 0x0: 1151 return new Sxth(machInst, rd, 0, rm); 1152 case 0x1: 1153 return new Sxtb(machInst, rd, 0, rm); 1154 case 0x2: 1155 return new Uxth(machInst, rd, 0, rm); 1156 case 0x3: 1157 return new Uxtb(machInst, rd, 0, rm); 1158 } 1159 } | 1138 case 0x2: 1139 { 1140 const IntRegIndex rd = 1141 (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 1142 const IntRegIndex rm = 1143 (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 1144 switch (bits(machInst, 7, 6)) { 1145 case 0x0: 1146 return new Sxth(machInst, rd, 0, rm); 1147 case 0x1: 1148 return new Sxtb(machInst, rd, 0, rm); 1149 case 0x2: 1150 return new Uxth(machInst, rd, 0, rm); 1151 case 0x3: 1152 return new Uxtb(machInst, rd, 0, rm); 1153 } 1154 } |
1155 case 0x1: |
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1160 case 0x3: 1161 return new Cbz(machInst, 1162 (bits(machInst, 9) << 6) | 1163 (bits(machInst, 7, 3) << 1), 1164 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1165 case 0x4: 1166 case 0x5: 1167 { --- 9 unchanged lines hidden (view full) --- 1177 return new Setend(machInst, bits(machInst, 3)); 1178 } else if (opBits == 3) { 1179 const bool enable = (bits(machInst, 4) == 0); 1180 const uint32_t mods = (bits(machInst, 2, 0) << 5) | 1181 ((enable ? 1 : 0) << 9); 1182 return new Cps(machInst, mods); 1183 } 1184 } | 1156 case 0x3: 1157 return new Cbz(machInst, 1158 (bits(machInst, 9) << 6) | 1159 (bits(machInst, 7, 3) << 1), 1160 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1161 case 0x4: 1162 case 0x5: 1163 { --- 9 unchanged lines hidden (view full) --- 1173 return new Setend(machInst, bits(machInst, 3)); 1174 } else if (opBits == 3) { 1175 const bool enable = (bits(machInst, 4) == 0); 1176 const uint32_t mods = (bits(machInst, 2, 0) << 5) | 1177 ((enable ? 1 : 0) << 9); 1178 return new Cps(machInst, mods); 1179 } 1180 } |
1185 case 0x9: 1186 return new Cbnz(machInst, 1187 (bits(machInst, 9) << 6) | 1188 (bits(machInst, 7, 3) << 1), 1189 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); | |
1190 case 0xa: 1191 { 1192 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 1193 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 1194 switch (bits(machInst, 7, 6)) { 1195 case 0x0: 1196 return new Rev(machInst, rd, rm); 1197 case 0x1: 1198 return new Rev16(machInst, rd, rm); 1199 case 0x3: 1200 return new Revsh(machInst, rd, rm); 1201 default: 1202 break; 1203 } 1204 } 1205 break; | 1181 case 0xa: 1182 { 1183 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 1184 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 1185 switch (bits(machInst, 7, 6)) { 1186 case 0x0: 1187 return new Rev(machInst, rd, rm); 1188 case 0x1: 1189 return new Rev16(machInst, rd, rm); 1190 case 0x3: 1191 return new Revsh(machInst, rd, rm); 1192 default: 1193 break; 1194 } 1195 } 1196 break; |
1197 case 0x9: |
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1206 case 0xb: 1207 return new Cbnz(machInst, 1208 (bits(machInst, 9) << 6) | 1209 (bits(machInst, 7, 3) << 1), 1210 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1211 case 0xc: 1212 case 0xd: 1213 { --- 331 unchanged lines hidden --- | 1198 case 0xb: 1199 return new Cbnz(machInst, 1200 (bits(machInst, 9) << 6) | 1201 (bits(machInst, 7, 3) << 1), 1202 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1203 case 0xc: 1204 case 0xd: 1205 { --- 331 unchanged lines hidden --- |