crypto64.isa (13170:eb0a1f32798d) crypto64.isa (13171:8d3d2b1f1ca3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 26 unchanged lines hidden (view full) ---

35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Giacomo Travaglini
39
40let {{
41 header_output = '''
42 StaticInstPtr
1// -*- mode:c++ -*-
2
3// Copyright (c) 2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 26 unchanged lines hidden (view full) ---

35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Giacomo Travaglini
39
40let {{
41 header_output = '''
42 StaticInstPtr
43 decodeCryptoAES(ExtMachInst machInst);
44
45 StaticInstPtr
43 decodeCryptoThreeRegSHA(ExtMachInst machInst);
44
45 StaticInstPtr
46 decodeCryptoTwoRegSHA(ExtMachInst machInst);
47 '''
48
49 decoder_output = '''
50
51 StaticInstPtr
46 decodeCryptoThreeRegSHA(ExtMachInst machInst);
47
48 StaticInstPtr
49 decodeCryptoTwoRegSHA(ExtMachInst machInst);
50 '''
51
52 decoder_output = '''
53
54 StaticInstPtr
55 decodeCryptoAES(ExtMachInst machInst)
56 {
57 const auto opcode = bits(machInst, 16, 12);
58 const auto size = bits(machInst, 23, 22);
59
60 IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
61 IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
62
63 if (size) {
64 // UNALLOCATED
65 return new Unknown64(machInst);
66 } else {
67 switch (opcode) {
68 case 0x4: return new AESE64(machInst, rd, rd, rn);
69 case 0x5: return new AESD64(machInst, rd, rd, rn);
70 case 0x6: return new AESMC64(machInst, rd, rn);
71 case 0x7: return new AESIMC64(machInst, rd, rn);
72 default: return new Unknown64(machInst);
73 }
74 }
75 }
76
77 StaticInstPtr
52 decodeCryptoTwoRegSHA(ExtMachInst machInst)
53 {
54 const auto opcode = bits(machInst, 16, 12);
55 const auto size = bits(machInst, 23, 22);
56
57 IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
58 IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
59

--- 41 unchanged lines hidden --- 		78 decodeCryptoTwoRegSHA(ExtMachInst machInst)
79 {
80 const auto opcode = bits(machInst, 16, 12);
81 const auto size = bits(machInst, 23, 22);
82
83 IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
84 IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
85

--- 41 unchanged lines hidden ---