intregs.hh (6726:a5322e816a2a) | intregs.hh (6734:4ac7bc30c482) |
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1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 49 unchanged lines hidden (view full) --- 58 INTREG_LR = INTREG_R14, 59 INTREG_R15, 60 INTREG_PC = INTREG_R15, 61 62 INTREG_R13_SVC, 63 INTREG_SP_SVC = INTREG_R13_SVC, 64 INTREG_R14_SVC, 65 INTREG_LR_SVC = INTREG_R14_SVC, | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 49 unchanged lines hidden (view full) --- 58 INTREG_LR = INTREG_R14, 59 INTREG_R15, 60 INTREG_PC = INTREG_R15, 61 62 INTREG_R13_SVC, 63 INTREG_SP_SVC = INTREG_R13_SVC, 64 INTREG_R14_SVC, 65 INTREG_LR_SVC = INTREG_R14_SVC, |
66 INTREG_R15_SVC = INTREG_R15, | |
67 68 INTREG_R13_MON, 69 INTREG_SP_MON = INTREG_R13_MON, 70 INTREG_R14_MON, 71 INTREG_LR_MON = INTREG_R14_MON, | 66 67 INTREG_R13_MON, 68 INTREG_SP_MON = INTREG_R13_MON, 69 INTREG_R14_MON, 70 INTREG_LR_MON = INTREG_R14_MON, |
72 INTREG_R15_MON = INTREG_R15, | |
73 74 INTREG_R13_ABT, 75 INTREG_SP_ABT = INTREG_R13_ABT, 76 INTREG_R14_ABT, 77 INTREG_LR_ABT = INTREG_R14_ABT, | 71 72 INTREG_R13_ABT, 73 INTREG_SP_ABT = INTREG_R13_ABT, 74 INTREG_R14_ABT, 75 INTREG_LR_ABT = INTREG_R14_ABT, |
78 INTREG_R15_ABT = INTREG_R15, | |
79 80 INTREG_R13_UND, 81 INTREG_SP_UND = INTREG_R13_UND, 82 INTREG_R14_UND, 83 INTREG_LR_UND = INTREG_R14_UND, | 76 77 INTREG_R13_UND, 78 INTREG_SP_UND = INTREG_R13_UND, 79 INTREG_R14_UND, 80 INTREG_LR_UND = INTREG_R14_UND, |
84 INTREG_R15_UND = INTREG_R15, | |
85 86 INTREG_R13_IRQ, 87 INTREG_SP_IRQ = INTREG_R13_IRQ, 88 INTREG_R14_IRQ, 89 INTREG_LR_IRQ = INTREG_R14_IRQ, | 81 82 INTREG_R13_IRQ, 83 INTREG_SP_IRQ = INTREG_R13_IRQ, 84 INTREG_R14_IRQ, 85 INTREG_LR_IRQ = INTREG_R14_IRQ, |
90 INTREG_R15_IRQ = INTREG_R15, | |
91 92 INTREG_R8_FIQ, 93 INTREG_R9_FIQ, 94 INTREG_R10_FIQ, 95 INTREG_R11_FIQ, 96 INTREG_R12_FIQ, 97 INTREG_R13_FIQ, 98 INTREG_SP_FIQ = INTREG_R13_FIQ, 99 INTREG_R14_FIQ, 100 INTREG_LR_FIQ = INTREG_R14_FIQ, | 86 87 INTREG_R8_FIQ, 88 INTREG_R9_FIQ, 89 INTREG_R10_FIQ, 90 INTREG_R11_FIQ, 91 INTREG_R12_FIQ, 92 INTREG_R13_FIQ, 93 INTREG_SP_FIQ = INTREG_R13_FIQ, 94 INTREG_R14_FIQ, 95 INTREG_LR_FIQ = INTREG_R14_FIQ, |
101 INTREG_R15_FIQ = INTREG_R15, | |
102 103 INTREG_ZERO, // Dummy zero reg since there has to be one. 104 INTREG_UREG0, 105 INTREG_RHI, 106 INTREG_RLO, 107 INTREG_CONDCODES, 108 109 NUM_INTREGS, --- 32 unchanged lines hidden (view full) --- 142 INTREG_R6_SVC = INTREG_R6, 143 INTREG_R7_SVC = INTREG_R7, 144 INTREG_R8_SVC = INTREG_R8, 145 INTREG_R9_SVC = INTREG_R9, 146 INTREG_R10_SVC = INTREG_R10, 147 INTREG_R11_SVC = INTREG_R11, 148 INTREG_R12_SVC = INTREG_R12, 149 INTREG_PC_SVC = INTREG_PC, | 96 97 INTREG_ZERO, // Dummy zero reg since there has to be one. 98 INTREG_UREG0, 99 INTREG_RHI, 100 INTREG_RLO, 101 INTREG_CONDCODES, 102 103 NUM_INTREGS, --- 32 unchanged lines hidden (view full) --- 136 INTREG_R6_SVC = INTREG_R6, 137 INTREG_R7_SVC = INTREG_R7, 138 INTREG_R8_SVC = INTREG_R8, 139 INTREG_R9_SVC = INTREG_R9, 140 INTREG_R10_SVC = INTREG_R10, 141 INTREG_R11_SVC = INTREG_R11, 142 INTREG_R12_SVC = INTREG_R12, 143 INTREG_PC_SVC = INTREG_PC, |
144 INTREG_R15_SVC = INTREG_R15, |
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150 151 /* MON mode */ 152 INTREG_R0_MON = INTREG_R0, 153 INTREG_R1_MON = INTREG_R1, 154 INTREG_R2_MON = INTREG_R2, 155 INTREG_R3_MON = INTREG_R3, 156 INTREG_R4_MON = INTREG_R4, 157 INTREG_R5_MON = INTREG_R5, 158 INTREG_R6_MON = INTREG_R6, 159 INTREG_R7_MON = INTREG_R7, 160 INTREG_R8_MON = INTREG_R8, 161 INTREG_R9_MON = INTREG_R9, 162 INTREG_R10_MON = INTREG_R10, 163 INTREG_R11_MON = INTREG_R11, 164 INTREG_R12_MON = INTREG_R12, 165 INTREG_PC_MON = INTREG_PC, | 145 146 /* MON mode */ 147 INTREG_R0_MON = INTREG_R0, 148 INTREG_R1_MON = INTREG_R1, 149 INTREG_R2_MON = INTREG_R2, 150 INTREG_R3_MON = INTREG_R3, 151 INTREG_R4_MON = INTREG_R4, 152 INTREG_R5_MON = INTREG_R5, 153 INTREG_R6_MON = INTREG_R6, 154 INTREG_R7_MON = INTREG_R7, 155 INTREG_R8_MON = INTREG_R8, 156 INTREG_R9_MON = INTREG_R9, 157 INTREG_R10_MON = INTREG_R10, 158 INTREG_R11_MON = INTREG_R11, 159 INTREG_R12_MON = INTREG_R12, 160 INTREG_PC_MON = INTREG_PC, |
161 INTREG_R15_MON = INTREG_R15, |
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166 167 /* ABT mode */ 168 INTREG_R0_ABT = INTREG_R0, 169 INTREG_R1_ABT = INTREG_R1, 170 INTREG_R2_ABT = INTREG_R2, 171 INTREG_R3_ABT = INTREG_R3, 172 INTREG_R4_ABT = INTREG_R4, 173 INTREG_R5_ABT = INTREG_R5, 174 INTREG_R6_ABT = INTREG_R6, 175 INTREG_R7_ABT = INTREG_R7, 176 INTREG_R8_ABT = INTREG_R8, 177 INTREG_R9_ABT = INTREG_R9, 178 INTREG_R10_ABT = INTREG_R10, 179 INTREG_R11_ABT = INTREG_R11, 180 INTREG_R12_ABT = INTREG_R12, 181 INTREG_PC_ABT = INTREG_PC, | 162 163 /* ABT mode */ 164 INTREG_R0_ABT = INTREG_R0, 165 INTREG_R1_ABT = INTREG_R1, 166 INTREG_R2_ABT = INTREG_R2, 167 INTREG_R3_ABT = INTREG_R3, 168 INTREG_R4_ABT = INTREG_R4, 169 INTREG_R5_ABT = INTREG_R5, 170 INTREG_R6_ABT = INTREG_R6, 171 INTREG_R7_ABT = INTREG_R7, 172 INTREG_R8_ABT = INTREG_R8, 173 INTREG_R9_ABT = INTREG_R9, 174 INTREG_R10_ABT = INTREG_R10, 175 INTREG_R11_ABT = INTREG_R11, 176 INTREG_R12_ABT = INTREG_R12, 177 INTREG_PC_ABT = INTREG_PC, |
178 INTREG_R15_ABT = INTREG_R15, |
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182 183 /* UND mode */ 184 INTREG_R0_UND = INTREG_R0, 185 INTREG_R1_UND = INTREG_R1, 186 INTREG_R2_UND = INTREG_R2, 187 INTREG_R3_UND = INTREG_R3, 188 INTREG_R4_UND = INTREG_R4, 189 INTREG_R5_UND = INTREG_R5, 190 INTREG_R6_UND = INTREG_R6, 191 INTREG_R7_UND = INTREG_R7, 192 INTREG_R8_UND = INTREG_R8, 193 INTREG_R9_UND = INTREG_R9, 194 INTREG_R10_UND = INTREG_R10, 195 INTREG_R11_UND = INTREG_R11, 196 INTREG_R12_UND = INTREG_R12, 197 INTREG_PC_UND = INTREG_PC, | 179 180 /* UND mode */ 181 INTREG_R0_UND = INTREG_R0, 182 INTREG_R1_UND = INTREG_R1, 183 INTREG_R2_UND = INTREG_R2, 184 INTREG_R3_UND = INTREG_R3, 185 INTREG_R4_UND = INTREG_R4, 186 INTREG_R5_UND = INTREG_R5, 187 INTREG_R6_UND = INTREG_R6, 188 INTREG_R7_UND = INTREG_R7, 189 INTREG_R8_UND = INTREG_R8, 190 INTREG_R9_UND = INTREG_R9, 191 INTREG_R10_UND = INTREG_R10, 192 INTREG_R11_UND = INTREG_R11, 193 INTREG_R12_UND = INTREG_R12, 194 INTREG_PC_UND = INTREG_PC, |
195 INTREG_R15_UND = INTREG_R15, |
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198 199 /* IRQ mode */ 200 INTREG_R0_IRQ = INTREG_R0, 201 INTREG_R1_IRQ = INTREG_R1, 202 INTREG_R2_IRQ = INTREG_R2, 203 INTREG_R3_IRQ = INTREG_R3, 204 INTREG_R4_IRQ = INTREG_R4, 205 INTREG_R5_IRQ = INTREG_R5, 206 INTREG_R6_IRQ = INTREG_R6, 207 INTREG_R7_IRQ = INTREG_R7, 208 INTREG_R8_IRQ = INTREG_R8, 209 INTREG_R9_IRQ = INTREG_R9, 210 INTREG_R10_IRQ = INTREG_R10, 211 INTREG_R11_IRQ = INTREG_R11, 212 INTREG_R12_IRQ = INTREG_R12, 213 INTREG_PC_IRQ = INTREG_PC, | 196 197 /* IRQ mode */ 198 INTREG_R0_IRQ = INTREG_R0, 199 INTREG_R1_IRQ = INTREG_R1, 200 INTREG_R2_IRQ = INTREG_R2, 201 INTREG_R3_IRQ = INTREG_R3, 202 INTREG_R4_IRQ = INTREG_R4, 203 INTREG_R5_IRQ = INTREG_R5, 204 INTREG_R6_IRQ = INTREG_R6, 205 INTREG_R7_IRQ = INTREG_R7, 206 INTREG_R8_IRQ = INTREG_R8, 207 INTREG_R9_IRQ = INTREG_R9, 208 INTREG_R10_IRQ = INTREG_R10, 209 INTREG_R11_IRQ = INTREG_R11, 210 INTREG_R12_IRQ = INTREG_R12, 211 INTREG_PC_IRQ = INTREG_PC, |
212 INTREG_R15_IRQ = INTREG_R15, |
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214 215 /* FIQ mode */ 216 INTREG_R0_FIQ = INTREG_R0, 217 INTREG_R1_FIQ = INTREG_R1, 218 INTREG_R2_FIQ = INTREG_R2, 219 INTREG_R3_FIQ = INTREG_R3, 220 INTREG_R4_FIQ = INTREG_R4, 221 INTREG_R5_FIQ = INTREG_R5, 222 INTREG_R6_FIQ = INTREG_R6, 223 INTREG_R7_FIQ = INTREG_R7, 224 INTREG_PC_FIQ = INTREG_PC, | 213 214 /* FIQ mode */ 215 INTREG_R0_FIQ = INTREG_R0, 216 INTREG_R1_FIQ = INTREG_R1, 217 INTREG_R2_FIQ = INTREG_R2, 218 INTREG_R3_FIQ = INTREG_R3, 219 INTREG_R4_FIQ = INTREG_R4, 220 INTREG_R5_FIQ = INTREG_R5, 221 INTREG_R6_FIQ = INTREG_R6, 222 INTREG_R7_FIQ = INTREG_R7, 223 INTREG_PC_FIQ = INTREG_PC, |
224 INTREG_R15_FIQ = INTREG_R15, |
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225}; 226 227typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS]; 228 229const IntRegMap IntRegUsrMap = { 230 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR, 231 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR, 232 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR, --- 90 unchanged lines hidden (view full) --- 323 assert(index < NUM_ARCH_INTREGS); 324 return IntRegFiqMap[index]; 325} 326 327static inline IntRegIndex 328intRegForceUser(unsigned index) 329{ 330 assert(index < NUM_ARCH_INTREGS); | 225}; 226 227typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS]; 228 229const IntRegMap IntRegUsrMap = { 230 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR, 231 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR, 232 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR, --- 90 unchanged lines hidden (view full) --- 323 assert(index < NUM_ARCH_INTREGS); 324 return IntRegFiqMap[index]; 325} 326 327static inline IntRegIndex 328intRegForceUser(unsigned index) 329{ 330 assert(index < NUM_ARCH_INTREGS); |
331 return (IntRegIndex)(index + NUM_INTREGS); | 331 332 return index == 15 ? (IntRegIndex)15 : (IntRegIndex)(index + NUM_INTREGS); |
332} 333 334} 335 336#endif | 333} 334 335} 336 337#endif |