1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include <assert.h>
44
45#ifndef __ARCH_ARM_INTREGS_HH__
46#define __ARCH_ARM_INTREGS_HH__
47
48#include "arch/arm/types.hh"
49
50namespace ArmISA
51{
52
53enum IntRegIndex
54{
55 /* All the unique register indices. */
56 INTREG_R0,
57 INTREG_R1,
58 INTREG_R2,
59 INTREG_R3,
60 INTREG_R4,
61 INTREG_R5,
62 INTREG_R6,
63 INTREG_R7,
64 INTREG_R8,
65 INTREG_R9,
66 INTREG_R10,
67 INTREG_R11,
68 INTREG_R12,
69 INTREG_R13,
70 INTREG_SP = INTREG_R13,
71 INTREG_R14,
72 INTREG_LR = INTREG_R14,
73 INTREG_R15,
74 INTREG_PC = INTREG_R15,
75
76 INTREG_R13_SVC,
77 INTREG_SP_SVC = INTREG_R13_SVC,
78 INTREG_R14_SVC,
79 INTREG_LR_SVC = INTREG_R14_SVC,
80
81 INTREG_R13_MON,
82 INTREG_SP_MON = INTREG_R13_MON,
83 INTREG_R14_MON,
84 INTREG_LR_MON = INTREG_R14_MON,
85
86 INTREG_R13_ABT,
87 INTREG_SP_ABT = INTREG_R13_ABT,
88 INTREG_R14_ABT,
89 INTREG_LR_ABT = INTREG_R14_ABT,
90
91 INTREG_R13_UND,
92 INTREG_SP_UND = INTREG_R13_UND,
93 INTREG_R14_UND,
94 INTREG_LR_UND = INTREG_R14_UND,
95
96 INTREG_R13_IRQ,
97 INTREG_SP_IRQ = INTREG_R13_IRQ,
98 INTREG_R14_IRQ,
99 INTREG_LR_IRQ = INTREG_R14_IRQ,
100
101 INTREG_R8_FIQ,
102 INTREG_R9_FIQ,
103 INTREG_R10_FIQ,
104 INTREG_R11_FIQ,
105 INTREG_R12_FIQ,
106 INTREG_R13_FIQ,
107 INTREG_SP_FIQ = INTREG_R13_FIQ,
108 INTREG_R14_FIQ,
109 INTREG_LR_FIQ = INTREG_R14_FIQ,
110
111 INTREG_ZERO, // Dummy zero reg since there has to be one.
112 INTREG_UREG0,
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include <assert.h>
44
45#ifndef __ARCH_ARM_INTREGS_HH__
46#define __ARCH_ARM_INTREGS_HH__
47
48#include "arch/arm/types.hh"
49
50namespace ArmISA
51{
52
53enum IntRegIndex
54{
55 /* All the unique register indices. */
56 INTREG_R0,
57 INTREG_R1,
58 INTREG_R2,
59 INTREG_R3,
60 INTREG_R4,
61 INTREG_R5,
62 INTREG_R6,
63 INTREG_R7,
64 INTREG_R8,
65 INTREG_R9,
66 INTREG_R10,
67 INTREG_R11,
68 INTREG_R12,
69 INTREG_R13,
70 INTREG_SP = INTREG_R13,
71 INTREG_R14,
72 INTREG_LR = INTREG_R14,
73 INTREG_R15,
74 INTREG_PC = INTREG_R15,
75
76 INTREG_R13_SVC,
77 INTREG_SP_SVC = INTREG_R13_SVC,
78 INTREG_R14_SVC,
79 INTREG_LR_SVC = INTREG_R14_SVC,
80
81 INTREG_R13_MON,
82 INTREG_SP_MON = INTREG_R13_MON,
83 INTREG_R14_MON,
84 INTREG_LR_MON = INTREG_R14_MON,
85
86 INTREG_R13_ABT,
87 INTREG_SP_ABT = INTREG_R13_ABT,
88 INTREG_R14_ABT,
89 INTREG_LR_ABT = INTREG_R14_ABT,
90
91 INTREG_R13_UND,
92 INTREG_SP_UND = INTREG_R13_UND,
93 INTREG_R14_UND,
94 INTREG_LR_UND = INTREG_R14_UND,
95
96 INTREG_R13_IRQ,
97 INTREG_SP_IRQ = INTREG_R13_IRQ,
98 INTREG_R14_IRQ,
99 INTREG_LR_IRQ = INTREG_R14_IRQ,
100
101 INTREG_R8_FIQ,
102 INTREG_R9_FIQ,
103 INTREG_R10_FIQ,
104 INTREG_R11_FIQ,
105 INTREG_R12_FIQ,
106 INTREG_R13_FIQ,
107 INTREG_SP_FIQ = INTREG_R13_FIQ,
108 INTREG_R14_FIQ,
109 INTREG_LR_FIQ = INTREG_R14_FIQ,
110
111 INTREG_ZERO, // Dummy zero reg since there has to be one.
112 INTREG_UREG0,
|
113 INTREG_CONDCODES,
114 INTREG_FPCONDCODES,
115
116 NUM_INTREGS,
117 NUM_ARCH_INTREGS = INTREG_PC + 1,
118
119 /* All the aliased indexes. */
120
121 /* USR mode */
122 INTREG_R0_USR = INTREG_R0,
123 INTREG_R1_USR = INTREG_R1,
124 INTREG_R2_USR = INTREG_R2,
125 INTREG_R3_USR = INTREG_R3,
126 INTREG_R4_USR = INTREG_R4,
127 INTREG_R5_USR = INTREG_R5,
128 INTREG_R6_USR = INTREG_R6,
129 INTREG_R7_USR = INTREG_R7,
130 INTREG_R8_USR = INTREG_R8,
131 INTREG_R9_USR = INTREG_R9,
132 INTREG_R10_USR = INTREG_R10,
133 INTREG_R11_USR = INTREG_R11,
134 INTREG_R12_USR = INTREG_R12,
135 INTREG_R13_USR = INTREG_R13,
136 INTREG_SP_USR = INTREG_SP,
137 INTREG_R14_USR = INTREG_R14,
138 INTREG_LR_USR = INTREG_LR,
139 INTREG_R15_USR = INTREG_R15,
140 INTREG_PC_USR = INTREG_PC,
141
142 /* SVC mode */
143 INTREG_R0_SVC = INTREG_R0,
144 INTREG_R1_SVC = INTREG_R1,
145 INTREG_R2_SVC = INTREG_R2,
146 INTREG_R3_SVC = INTREG_R3,
147 INTREG_R4_SVC = INTREG_R4,
148 INTREG_R5_SVC = INTREG_R5,
149 INTREG_R6_SVC = INTREG_R6,
150 INTREG_R7_SVC = INTREG_R7,
151 INTREG_R8_SVC = INTREG_R8,
152 INTREG_R9_SVC = INTREG_R9,
153 INTREG_R10_SVC = INTREG_R10,
154 INTREG_R11_SVC = INTREG_R11,
155 INTREG_R12_SVC = INTREG_R12,
156 INTREG_PC_SVC = INTREG_PC,
157 INTREG_R15_SVC = INTREG_R15,
158
159 /* MON mode */
160 INTREG_R0_MON = INTREG_R0,
161 INTREG_R1_MON = INTREG_R1,
162 INTREG_R2_MON = INTREG_R2,
163 INTREG_R3_MON = INTREG_R3,
164 INTREG_R4_MON = INTREG_R4,
165 INTREG_R5_MON = INTREG_R5,
166 INTREG_R6_MON = INTREG_R6,
167 INTREG_R7_MON = INTREG_R7,
168 INTREG_R8_MON = INTREG_R8,
169 INTREG_R9_MON = INTREG_R9,
170 INTREG_R10_MON = INTREG_R10,
171 INTREG_R11_MON = INTREG_R11,
172 INTREG_R12_MON = INTREG_R12,
173 INTREG_PC_MON = INTREG_PC,
174 INTREG_R15_MON = INTREG_R15,
175
176 /* ABT mode */
177 INTREG_R0_ABT = INTREG_R0,
178 INTREG_R1_ABT = INTREG_R1,
179 INTREG_R2_ABT = INTREG_R2,
180 INTREG_R3_ABT = INTREG_R3,
181 INTREG_R4_ABT = INTREG_R4,
182 INTREG_R5_ABT = INTREG_R5,
183 INTREG_R6_ABT = INTREG_R6,
184 INTREG_R7_ABT = INTREG_R7,
185 INTREG_R8_ABT = INTREG_R8,
186 INTREG_R9_ABT = INTREG_R9,
187 INTREG_R10_ABT = INTREG_R10,
188 INTREG_R11_ABT = INTREG_R11,
189 INTREG_R12_ABT = INTREG_R12,
190 INTREG_PC_ABT = INTREG_PC,
191 INTREG_R15_ABT = INTREG_R15,
192
193 /* UND mode */
194 INTREG_R0_UND = INTREG_R0,
195 INTREG_R1_UND = INTREG_R1,
196 INTREG_R2_UND = INTREG_R2,
197 INTREG_R3_UND = INTREG_R3,
198 INTREG_R4_UND = INTREG_R4,
199 INTREG_R5_UND = INTREG_R5,
200 INTREG_R6_UND = INTREG_R6,
201 INTREG_R7_UND = INTREG_R7,
202 INTREG_R8_UND = INTREG_R8,
203 INTREG_R9_UND = INTREG_R9,
204 INTREG_R10_UND = INTREG_R10,
205 INTREG_R11_UND = INTREG_R11,
206 INTREG_R12_UND = INTREG_R12,
207 INTREG_PC_UND = INTREG_PC,
208 INTREG_R15_UND = INTREG_R15,
209
210 /* IRQ mode */
211 INTREG_R0_IRQ = INTREG_R0,
212 INTREG_R1_IRQ = INTREG_R1,
213 INTREG_R2_IRQ = INTREG_R2,
214 INTREG_R3_IRQ = INTREG_R3,
215 INTREG_R4_IRQ = INTREG_R4,
216 INTREG_R5_IRQ = INTREG_R5,
217 INTREG_R6_IRQ = INTREG_R6,
218 INTREG_R7_IRQ = INTREG_R7,
219 INTREG_R8_IRQ = INTREG_R8,
220 INTREG_R9_IRQ = INTREG_R9,
221 INTREG_R10_IRQ = INTREG_R10,
222 INTREG_R11_IRQ = INTREG_R11,
223 INTREG_R12_IRQ = INTREG_R12,
224 INTREG_PC_IRQ = INTREG_PC,
225 INTREG_R15_IRQ = INTREG_R15,
226
227 /* FIQ mode */
228 INTREG_R0_FIQ = INTREG_R0,
229 INTREG_R1_FIQ = INTREG_R1,
230 INTREG_R2_FIQ = INTREG_R2,
231 INTREG_R3_FIQ = INTREG_R3,
232 INTREG_R4_FIQ = INTREG_R4,
233 INTREG_R5_FIQ = INTREG_R5,
234 INTREG_R6_FIQ = INTREG_R6,
235 INTREG_R7_FIQ = INTREG_R7,
236 INTREG_PC_FIQ = INTREG_PC,
237 INTREG_R15_FIQ = INTREG_R15,
238};
239
240typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
241
242const IntRegMap IntRegUsrMap = {
243 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
244 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
245 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
246 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
247};
248
249static inline IntRegIndex
250INTREG_USR(unsigned index)
251{
252 assert(index < NUM_ARCH_INTREGS);
253 return IntRegUsrMap[index];
254}
255
256const IntRegMap IntRegSvcMap = {
257 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
258 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
259 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
260 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
261};
262
263static inline IntRegIndex
264INTREG_SVC(unsigned index)
265{
266 assert(index < NUM_ARCH_INTREGS);
267 return IntRegSvcMap[index];
268}
269
270const IntRegMap IntRegMonMap = {
271 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
272 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
273 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
274 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
275};
276
277static inline IntRegIndex
278INTREG_MON(unsigned index)
279{
280 assert(index < NUM_ARCH_INTREGS);
281 return IntRegMonMap[index];
282}
283
284const IntRegMap IntRegAbtMap = {
285 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
286 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
287 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
288 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
289};
290
291static inline IntRegIndex
292INTREG_ABT(unsigned index)
293{
294 assert(index < NUM_ARCH_INTREGS);
295 return IntRegAbtMap[index];
296}
297
298const IntRegMap IntRegUndMap = {
299 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
300 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
301 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
302 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
303};
304
305static inline IntRegIndex
306INTREG_UND(unsigned index)
307{
308 assert(index < NUM_ARCH_INTREGS);
309 return IntRegUndMap[index];
310}
311
312const IntRegMap IntRegIrqMap = {
313 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
314 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
315 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
316 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
317};
318
319static inline IntRegIndex
320INTREG_IRQ(unsigned index)
321{
322 assert(index < NUM_ARCH_INTREGS);
323 return IntRegIrqMap[index];
324}
325
326const IntRegMap IntRegFiqMap = {
327 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
328 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
329 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
330 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
331};
332
333static inline IntRegIndex
334INTREG_FIQ(unsigned index)
335{
336 assert(index < NUM_ARCH_INTREGS);
337 return IntRegFiqMap[index];
338}
339
340static const unsigned intRegsPerMode = NUM_INTREGS;
341
342static inline int
343intRegInMode(OperatingMode mode, int reg)
344{
345 assert(reg < NUM_ARCH_INTREGS);
346 return mode * intRegsPerMode + reg;
347}
348
349}
350
351#endif
| 115 INTREG_CONDCODES,
116 INTREG_FPCONDCODES,
117
118 NUM_INTREGS,
119 NUM_ARCH_INTREGS = INTREG_PC + 1,
120
121 /* All the aliased indexes. */
122
123 /* USR mode */
124 INTREG_R0_USR = INTREG_R0,
125 INTREG_R1_USR = INTREG_R1,
126 INTREG_R2_USR = INTREG_R2,
127 INTREG_R3_USR = INTREG_R3,
128 INTREG_R4_USR = INTREG_R4,
129 INTREG_R5_USR = INTREG_R5,
130 INTREG_R6_USR = INTREG_R6,
131 INTREG_R7_USR = INTREG_R7,
132 INTREG_R8_USR = INTREG_R8,
133 INTREG_R9_USR = INTREG_R9,
134 INTREG_R10_USR = INTREG_R10,
135 INTREG_R11_USR = INTREG_R11,
136 INTREG_R12_USR = INTREG_R12,
137 INTREG_R13_USR = INTREG_R13,
138 INTREG_SP_USR = INTREG_SP,
139 INTREG_R14_USR = INTREG_R14,
140 INTREG_LR_USR = INTREG_LR,
141 INTREG_R15_USR = INTREG_R15,
142 INTREG_PC_USR = INTREG_PC,
143
144 /* SVC mode */
145 INTREG_R0_SVC = INTREG_R0,
146 INTREG_R1_SVC = INTREG_R1,
147 INTREG_R2_SVC = INTREG_R2,
148 INTREG_R3_SVC = INTREG_R3,
149 INTREG_R4_SVC = INTREG_R4,
150 INTREG_R5_SVC = INTREG_R5,
151 INTREG_R6_SVC = INTREG_R6,
152 INTREG_R7_SVC = INTREG_R7,
153 INTREG_R8_SVC = INTREG_R8,
154 INTREG_R9_SVC = INTREG_R9,
155 INTREG_R10_SVC = INTREG_R10,
156 INTREG_R11_SVC = INTREG_R11,
157 INTREG_R12_SVC = INTREG_R12,
158 INTREG_PC_SVC = INTREG_PC,
159 INTREG_R15_SVC = INTREG_R15,
160
161 /* MON mode */
162 INTREG_R0_MON = INTREG_R0,
163 INTREG_R1_MON = INTREG_R1,
164 INTREG_R2_MON = INTREG_R2,
165 INTREG_R3_MON = INTREG_R3,
166 INTREG_R4_MON = INTREG_R4,
167 INTREG_R5_MON = INTREG_R5,
168 INTREG_R6_MON = INTREG_R6,
169 INTREG_R7_MON = INTREG_R7,
170 INTREG_R8_MON = INTREG_R8,
171 INTREG_R9_MON = INTREG_R9,
172 INTREG_R10_MON = INTREG_R10,
173 INTREG_R11_MON = INTREG_R11,
174 INTREG_R12_MON = INTREG_R12,
175 INTREG_PC_MON = INTREG_PC,
176 INTREG_R15_MON = INTREG_R15,
177
178 /* ABT mode */
179 INTREG_R0_ABT = INTREG_R0,
180 INTREG_R1_ABT = INTREG_R1,
181 INTREG_R2_ABT = INTREG_R2,
182 INTREG_R3_ABT = INTREG_R3,
183 INTREG_R4_ABT = INTREG_R4,
184 INTREG_R5_ABT = INTREG_R5,
185 INTREG_R6_ABT = INTREG_R6,
186 INTREG_R7_ABT = INTREG_R7,
187 INTREG_R8_ABT = INTREG_R8,
188 INTREG_R9_ABT = INTREG_R9,
189 INTREG_R10_ABT = INTREG_R10,
190 INTREG_R11_ABT = INTREG_R11,
191 INTREG_R12_ABT = INTREG_R12,
192 INTREG_PC_ABT = INTREG_PC,
193 INTREG_R15_ABT = INTREG_R15,
194
195 /* UND mode */
196 INTREG_R0_UND = INTREG_R0,
197 INTREG_R1_UND = INTREG_R1,
198 INTREG_R2_UND = INTREG_R2,
199 INTREG_R3_UND = INTREG_R3,
200 INTREG_R4_UND = INTREG_R4,
201 INTREG_R5_UND = INTREG_R5,
202 INTREG_R6_UND = INTREG_R6,
203 INTREG_R7_UND = INTREG_R7,
204 INTREG_R8_UND = INTREG_R8,
205 INTREG_R9_UND = INTREG_R9,
206 INTREG_R10_UND = INTREG_R10,
207 INTREG_R11_UND = INTREG_R11,
208 INTREG_R12_UND = INTREG_R12,
209 INTREG_PC_UND = INTREG_PC,
210 INTREG_R15_UND = INTREG_R15,
211
212 /* IRQ mode */
213 INTREG_R0_IRQ = INTREG_R0,
214 INTREG_R1_IRQ = INTREG_R1,
215 INTREG_R2_IRQ = INTREG_R2,
216 INTREG_R3_IRQ = INTREG_R3,
217 INTREG_R4_IRQ = INTREG_R4,
218 INTREG_R5_IRQ = INTREG_R5,
219 INTREG_R6_IRQ = INTREG_R6,
220 INTREG_R7_IRQ = INTREG_R7,
221 INTREG_R8_IRQ = INTREG_R8,
222 INTREG_R9_IRQ = INTREG_R9,
223 INTREG_R10_IRQ = INTREG_R10,
224 INTREG_R11_IRQ = INTREG_R11,
225 INTREG_R12_IRQ = INTREG_R12,
226 INTREG_PC_IRQ = INTREG_PC,
227 INTREG_R15_IRQ = INTREG_R15,
228
229 /* FIQ mode */
230 INTREG_R0_FIQ = INTREG_R0,
231 INTREG_R1_FIQ = INTREG_R1,
232 INTREG_R2_FIQ = INTREG_R2,
233 INTREG_R3_FIQ = INTREG_R3,
234 INTREG_R4_FIQ = INTREG_R4,
235 INTREG_R5_FIQ = INTREG_R5,
236 INTREG_R6_FIQ = INTREG_R6,
237 INTREG_R7_FIQ = INTREG_R7,
238 INTREG_PC_FIQ = INTREG_PC,
239 INTREG_R15_FIQ = INTREG_R15,
240};
241
242typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
243
244const IntRegMap IntRegUsrMap = {
245 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
246 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
247 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
248 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
249};
250
251static inline IntRegIndex
252INTREG_USR(unsigned index)
253{
254 assert(index < NUM_ARCH_INTREGS);
255 return IntRegUsrMap[index];
256}
257
258const IntRegMap IntRegSvcMap = {
259 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
260 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
261 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
262 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
263};
264
265static inline IntRegIndex
266INTREG_SVC(unsigned index)
267{
268 assert(index < NUM_ARCH_INTREGS);
269 return IntRegSvcMap[index];
270}
271
272const IntRegMap IntRegMonMap = {
273 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
274 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
275 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
276 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
277};
278
279static inline IntRegIndex
280INTREG_MON(unsigned index)
281{
282 assert(index < NUM_ARCH_INTREGS);
283 return IntRegMonMap[index];
284}
285
286const IntRegMap IntRegAbtMap = {
287 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
288 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
289 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
290 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
291};
292
293static inline IntRegIndex
294INTREG_ABT(unsigned index)
295{
296 assert(index < NUM_ARCH_INTREGS);
297 return IntRegAbtMap[index];
298}
299
300const IntRegMap IntRegUndMap = {
301 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
302 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
303 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
304 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
305};
306
307static inline IntRegIndex
308INTREG_UND(unsigned index)
309{
310 assert(index < NUM_ARCH_INTREGS);
311 return IntRegUndMap[index];
312}
313
314const IntRegMap IntRegIrqMap = {
315 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
316 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
317 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
318 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
319};
320
321static inline IntRegIndex
322INTREG_IRQ(unsigned index)
323{
324 assert(index < NUM_ARCH_INTREGS);
325 return IntRegIrqMap[index];
326}
327
328const IntRegMap IntRegFiqMap = {
329 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
330 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
331 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
332 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
333};
334
335static inline IntRegIndex
336INTREG_FIQ(unsigned index)
337{
338 assert(index < NUM_ARCH_INTREGS);
339 return IntRegFiqMap[index];
340}
341
342static const unsigned intRegsPerMode = NUM_INTREGS;
343
344static inline int
345intRegInMode(OperatingMode mode, int reg)
346{
347 assert(reg < NUM_ARCH_INTREGS);
348 return mode * intRegsPerMode + reg;
349}
350
351}
352
353#endif
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