1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include <assert.h>
32
33#ifndef __ARCH_ARM_INTREGS_HH__
34#define __ARCH_ARM_INTREGS_HH__
35
36namespace ArmISA
37{
38
39enum IntRegIndex
40{
41 /* All the unique register indices. */
42 INTREG_R0,
43 INTREG_R1,
44 INTREG_R2,
45 INTREG_R3,
46 INTREG_R4,
47 INTREG_R5,
48 INTREG_R6,
49 INTREG_R7,
50 INTREG_R8,
51 INTREG_R9,
52 INTREG_R10,
53 INTREG_R11,
54 INTREG_R12,
55 INTREG_R13,
56 INTREG_SP = INTREG_R13,
57 INTREG_R14,
58 INTREG_LR = INTREG_R14,
59 INTREG_R15,
60 INTREG_PC = INTREG_R15,
61
62 INTREG_R13_SVC,
63 INTREG_SP_SVC = INTREG_R13_SVC,
64 INTREG_R14_SVC,
65 INTREG_LR_SVC = INTREG_R14_SVC,
66 INTREG_R15_SVC = INTREG_R15,
67
68 INTREG_R13_MON,
69 INTREG_SP_MON = INTREG_R13_MON,
70 INTREG_R14_MON,
71 INTREG_LR_MON = INTREG_R14_MON,
72 INTREG_R15_MON = INTREG_R15,
73
74 INTREG_R13_ABT,
75 INTREG_SP_ABT = INTREG_R13_ABT,
76 INTREG_R14_ABT,
77 INTREG_LR_ABT = INTREG_R14_ABT,
78 INTREG_R15_ABT = INTREG_R15,
79
80 INTREG_R13_UND,
81 INTREG_SP_UND = INTREG_R13_UND,
82 INTREG_R14_UND,
83 INTREG_LR_UND = INTREG_R14_UND,
84 INTREG_R15_UND = INTREG_R15,
85
86 INTREG_R13_IRQ,
87 INTREG_SP_IRQ = INTREG_R13_IRQ,
88 INTREG_R14_IRQ,
89 INTREG_LR_IRQ = INTREG_R14_IRQ,
90 INTREG_R15_IRQ = INTREG_R15,
91
92 INTREG_R8_FIQ,
93 INTREG_R9_FIQ,
94 INTREG_R10_FIQ,
95 INTREG_R11_FIQ,
96 INTREG_R12_FIQ,
97 INTREG_R13_FIQ,
98 INTREG_SP_FIQ = INTREG_R13_FIQ,
99 INTREG_R14_FIQ,
100 INTREG_LR_FIQ = INTREG_R14_FIQ,
101 INTREG_R15_FIQ = INTREG_R15,
102
103 INTREG_ZERO, // Dummy zero reg since there has to be one.
104 INTREG_UREG0,
105 INTREG_RHI,
106 INTREG_RLO,
107 INTREG_CONDCODES,
108
109 NUM_INTREGS,
110 NUM_ARCH_INTREGS = INTREG_PC + 1,
111
112 /* All the aliased indexes. */
113
114 /* USR mode */
115 INTREG_R0_USR = INTREG_R0,
116 INTREG_R1_USR = INTREG_R1,
117 INTREG_R2_USR = INTREG_R2,
118 INTREG_R3_USR = INTREG_R3,
119 INTREG_R4_USR = INTREG_R4,
120 INTREG_R5_USR = INTREG_R5,
121 INTREG_R6_USR = INTREG_R6,
122 INTREG_R7_USR = INTREG_R7,
123 INTREG_R8_USR = INTREG_R8,
124 INTREG_R9_USR = INTREG_R9,
125 INTREG_R10_USR = INTREG_R10,
126 INTREG_R11_USR = INTREG_R11,
127 INTREG_R12_USR = INTREG_R12,
128 INTREG_R13_USR = INTREG_R13,
129 INTREG_SP_USR = INTREG_SP,
130 INTREG_R14_USR = INTREG_R14,
131 INTREG_LR_USR = INTREG_LR,
132 INTREG_R15_USR = INTREG_R15,
133 INTREG_PC_USR = INTREG_PC,
134
135 /* SVC mode */
136 INTREG_R0_SVC = INTREG_R0,
137 INTREG_R1_SVC = INTREG_R1,
138 INTREG_R2_SVC = INTREG_R2,
139 INTREG_R3_SVC = INTREG_R3,
140 INTREG_R4_SVC = INTREG_R4,
141 INTREG_R5_SVC = INTREG_R5,
142 INTREG_R6_SVC = INTREG_R6,
143 INTREG_R7_SVC = INTREG_R7,
144 INTREG_R8_SVC = INTREG_R8,
145 INTREG_R9_SVC = INTREG_R9,
146 INTREG_R10_SVC = INTREG_R10,
147 INTREG_R11_SVC = INTREG_R11,
148 INTREG_R12_SVC = INTREG_R12,
149 INTREG_PC_SVC = INTREG_PC,
150
151 /* MON mode */
152 INTREG_R0_MON = INTREG_R0,
153 INTREG_R1_MON = INTREG_R1,
154 INTREG_R2_MON = INTREG_R2,
155 INTREG_R3_MON = INTREG_R3,
156 INTREG_R4_MON = INTREG_R4,
157 INTREG_R5_MON = INTREG_R5,
158 INTREG_R6_MON = INTREG_R6,
159 INTREG_R7_MON = INTREG_R7,
160 INTREG_R8_MON = INTREG_R8,
161 INTREG_R9_MON = INTREG_R9,
162 INTREG_R10_MON = INTREG_R10,
163 INTREG_R11_MON = INTREG_R11,
164 INTREG_R12_MON = INTREG_R12,
165 INTREG_PC_MON = INTREG_PC,
166
167 /* ABT mode */
168 INTREG_R0_ABT = INTREG_R0,
169 INTREG_R1_ABT = INTREG_R1,
170 INTREG_R2_ABT = INTREG_R2,
171 INTREG_R3_ABT = INTREG_R3,
172 INTREG_R4_ABT = INTREG_R4,
173 INTREG_R5_ABT = INTREG_R5,
174 INTREG_R6_ABT = INTREG_R6,
175 INTREG_R7_ABT = INTREG_R7,
176 INTREG_R8_ABT = INTREG_R8,
177 INTREG_R9_ABT = INTREG_R9,
178 INTREG_R10_ABT = INTREG_R10,
179 INTREG_R11_ABT = INTREG_R11,
180 INTREG_R12_ABT = INTREG_R12,
181 INTREG_PC_ABT = INTREG_PC,
182
183 /* UND mode */
184 INTREG_R0_UND = INTREG_R0,
185 INTREG_R1_UND = INTREG_R1,
186 INTREG_R2_UND = INTREG_R2,
187 INTREG_R3_UND = INTREG_R3,
188 INTREG_R4_UND = INTREG_R4,
189 INTREG_R5_UND = INTREG_R5,
190 INTREG_R6_UND = INTREG_R6,
191 INTREG_R7_UND = INTREG_R7,
192 INTREG_R8_UND = INTREG_R8,
193 INTREG_R9_UND = INTREG_R9,
194 INTREG_R10_UND = INTREG_R10,
195 INTREG_R11_UND = INTREG_R11,
196 INTREG_R12_UND = INTREG_R12,
197 INTREG_PC_UND = INTREG_PC,
198
199 /* IRQ mode */
200 INTREG_R0_IRQ = INTREG_R0,
201 INTREG_R1_IRQ = INTREG_R1,
202 INTREG_R2_IRQ = INTREG_R2,
203 INTREG_R3_IRQ = INTREG_R3,
204 INTREG_R4_IRQ = INTREG_R4,
205 INTREG_R5_IRQ = INTREG_R5,
206 INTREG_R6_IRQ = INTREG_R6,
207 INTREG_R7_IRQ = INTREG_R7,
208 INTREG_R8_IRQ = INTREG_R8,
209 INTREG_R9_IRQ = INTREG_R9,
210 INTREG_R10_IRQ = INTREG_R10,
211 INTREG_R11_IRQ = INTREG_R11,
212 INTREG_R12_IRQ = INTREG_R12,
213 INTREG_PC_IRQ = INTREG_PC,
214
215 /* FIQ mode */
216 INTREG_R0_FIQ = INTREG_R0,
217 INTREG_R1_FIQ = INTREG_R1,
218 INTREG_R2_FIQ = INTREG_R2,
219 INTREG_R3_FIQ = INTREG_R3,
220 INTREG_R4_FIQ = INTREG_R4,
221 INTREG_R5_FIQ = INTREG_R5,
222 INTREG_R6_FIQ = INTREG_R6,
223 INTREG_R7_FIQ = INTREG_R7,
224 INTREG_PC_FIQ = INTREG_PC,
225};
226
227typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
228
229const IntRegMap IntRegUsrMap = {
230 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
231 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
232 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
233 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
234};
235
236static inline IntRegIndex
237INTREG_USR(unsigned index)
238{
239 assert(index < NUM_ARCH_INTREGS);
240 return IntRegUsrMap[index];
241}
242
243const IntRegMap IntRegSvcMap = {
244 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
245 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
246 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
247 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
248};
249
250static inline IntRegIndex
251INTREG_SVC(unsigned index)
252{
253 assert(index < NUM_ARCH_INTREGS);
254 return IntRegSvcMap[index];
255}
256
257const IntRegMap IntRegMonMap = {
258 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
259 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
260 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
261 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
262};
263
264static inline IntRegIndex
265INTREG_MON(unsigned index)
266{
267 assert(index < NUM_ARCH_INTREGS);
268 return IntRegMonMap[index];
269}
270
271const IntRegMap IntRegAbtMap = {
272 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
273 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
274 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
275 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
276};
277
278static inline IntRegIndex
279INTREG_ABT(unsigned index)
280{
281 assert(index < NUM_ARCH_INTREGS);
282 return IntRegAbtMap[index];
283}
284
285const IntRegMap IntRegUndMap = {
286 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
287 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
288 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
289 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
290};
291
292static inline IntRegIndex
293INTREG_UND(unsigned index)
294{
295 assert(index < NUM_ARCH_INTREGS);
296 return IntRegUndMap[index];
297}
298
299const IntRegMap IntRegIrqMap = {
300 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
301 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
302 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
303 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
304};
305
306static inline IntRegIndex
307INTREG_IRQ(unsigned index)
308{
309 assert(index < NUM_ARCH_INTREGS);
310 return IntRegIrqMap[index];
311}
312
313const IntRegMap IntRegFiqMap = {
314 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
315 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
316 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
317 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
318};
319
320static inline IntRegIndex
321INTREG_FIQ(unsigned index)
322{
323 assert(index < NUM_ARCH_INTREGS);
324 return IntRegFiqMap[index];
325}
326
| 1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include <assert.h>
32
33#ifndef __ARCH_ARM_INTREGS_HH__
34#define __ARCH_ARM_INTREGS_HH__
35
36namespace ArmISA
37{
38
39enum IntRegIndex
40{
41 /* All the unique register indices. */
42 INTREG_R0,
43 INTREG_R1,
44 INTREG_R2,
45 INTREG_R3,
46 INTREG_R4,
47 INTREG_R5,
48 INTREG_R6,
49 INTREG_R7,
50 INTREG_R8,
51 INTREG_R9,
52 INTREG_R10,
53 INTREG_R11,
54 INTREG_R12,
55 INTREG_R13,
56 INTREG_SP = INTREG_R13,
57 INTREG_R14,
58 INTREG_LR = INTREG_R14,
59 INTREG_R15,
60 INTREG_PC = INTREG_R15,
61
62 INTREG_R13_SVC,
63 INTREG_SP_SVC = INTREG_R13_SVC,
64 INTREG_R14_SVC,
65 INTREG_LR_SVC = INTREG_R14_SVC,
66 INTREG_R15_SVC = INTREG_R15,
67
68 INTREG_R13_MON,
69 INTREG_SP_MON = INTREG_R13_MON,
70 INTREG_R14_MON,
71 INTREG_LR_MON = INTREG_R14_MON,
72 INTREG_R15_MON = INTREG_R15,
73
74 INTREG_R13_ABT,
75 INTREG_SP_ABT = INTREG_R13_ABT,
76 INTREG_R14_ABT,
77 INTREG_LR_ABT = INTREG_R14_ABT,
78 INTREG_R15_ABT = INTREG_R15,
79
80 INTREG_R13_UND,
81 INTREG_SP_UND = INTREG_R13_UND,
82 INTREG_R14_UND,
83 INTREG_LR_UND = INTREG_R14_UND,
84 INTREG_R15_UND = INTREG_R15,
85
86 INTREG_R13_IRQ,
87 INTREG_SP_IRQ = INTREG_R13_IRQ,
88 INTREG_R14_IRQ,
89 INTREG_LR_IRQ = INTREG_R14_IRQ,
90 INTREG_R15_IRQ = INTREG_R15,
91
92 INTREG_R8_FIQ,
93 INTREG_R9_FIQ,
94 INTREG_R10_FIQ,
95 INTREG_R11_FIQ,
96 INTREG_R12_FIQ,
97 INTREG_R13_FIQ,
98 INTREG_SP_FIQ = INTREG_R13_FIQ,
99 INTREG_R14_FIQ,
100 INTREG_LR_FIQ = INTREG_R14_FIQ,
101 INTREG_R15_FIQ = INTREG_R15,
102
103 INTREG_ZERO, // Dummy zero reg since there has to be one.
104 INTREG_UREG0,
105 INTREG_RHI,
106 INTREG_RLO,
107 INTREG_CONDCODES,
108
109 NUM_INTREGS,
110 NUM_ARCH_INTREGS = INTREG_PC + 1,
111
112 /* All the aliased indexes. */
113
114 /* USR mode */
115 INTREG_R0_USR = INTREG_R0,
116 INTREG_R1_USR = INTREG_R1,
117 INTREG_R2_USR = INTREG_R2,
118 INTREG_R3_USR = INTREG_R3,
119 INTREG_R4_USR = INTREG_R4,
120 INTREG_R5_USR = INTREG_R5,
121 INTREG_R6_USR = INTREG_R6,
122 INTREG_R7_USR = INTREG_R7,
123 INTREG_R8_USR = INTREG_R8,
124 INTREG_R9_USR = INTREG_R9,
125 INTREG_R10_USR = INTREG_R10,
126 INTREG_R11_USR = INTREG_R11,
127 INTREG_R12_USR = INTREG_R12,
128 INTREG_R13_USR = INTREG_R13,
129 INTREG_SP_USR = INTREG_SP,
130 INTREG_R14_USR = INTREG_R14,
131 INTREG_LR_USR = INTREG_LR,
132 INTREG_R15_USR = INTREG_R15,
133 INTREG_PC_USR = INTREG_PC,
134
135 /* SVC mode */
136 INTREG_R0_SVC = INTREG_R0,
137 INTREG_R1_SVC = INTREG_R1,
138 INTREG_R2_SVC = INTREG_R2,
139 INTREG_R3_SVC = INTREG_R3,
140 INTREG_R4_SVC = INTREG_R4,
141 INTREG_R5_SVC = INTREG_R5,
142 INTREG_R6_SVC = INTREG_R6,
143 INTREG_R7_SVC = INTREG_R7,
144 INTREG_R8_SVC = INTREG_R8,
145 INTREG_R9_SVC = INTREG_R9,
146 INTREG_R10_SVC = INTREG_R10,
147 INTREG_R11_SVC = INTREG_R11,
148 INTREG_R12_SVC = INTREG_R12,
149 INTREG_PC_SVC = INTREG_PC,
150
151 /* MON mode */
152 INTREG_R0_MON = INTREG_R0,
153 INTREG_R1_MON = INTREG_R1,
154 INTREG_R2_MON = INTREG_R2,
155 INTREG_R3_MON = INTREG_R3,
156 INTREG_R4_MON = INTREG_R4,
157 INTREG_R5_MON = INTREG_R5,
158 INTREG_R6_MON = INTREG_R6,
159 INTREG_R7_MON = INTREG_R7,
160 INTREG_R8_MON = INTREG_R8,
161 INTREG_R9_MON = INTREG_R9,
162 INTREG_R10_MON = INTREG_R10,
163 INTREG_R11_MON = INTREG_R11,
164 INTREG_R12_MON = INTREG_R12,
165 INTREG_PC_MON = INTREG_PC,
166
167 /* ABT mode */
168 INTREG_R0_ABT = INTREG_R0,
169 INTREG_R1_ABT = INTREG_R1,
170 INTREG_R2_ABT = INTREG_R2,
171 INTREG_R3_ABT = INTREG_R3,
172 INTREG_R4_ABT = INTREG_R4,
173 INTREG_R5_ABT = INTREG_R5,
174 INTREG_R6_ABT = INTREG_R6,
175 INTREG_R7_ABT = INTREG_R7,
176 INTREG_R8_ABT = INTREG_R8,
177 INTREG_R9_ABT = INTREG_R9,
178 INTREG_R10_ABT = INTREG_R10,
179 INTREG_R11_ABT = INTREG_R11,
180 INTREG_R12_ABT = INTREG_R12,
181 INTREG_PC_ABT = INTREG_PC,
182
183 /* UND mode */
184 INTREG_R0_UND = INTREG_R0,
185 INTREG_R1_UND = INTREG_R1,
186 INTREG_R2_UND = INTREG_R2,
187 INTREG_R3_UND = INTREG_R3,
188 INTREG_R4_UND = INTREG_R4,
189 INTREG_R5_UND = INTREG_R5,
190 INTREG_R6_UND = INTREG_R6,
191 INTREG_R7_UND = INTREG_R7,
192 INTREG_R8_UND = INTREG_R8,
193 INTREG_R9_UND = INTREG_R9,
194 INTREG_R10_UND = INTREG_R10,
195 INTREG_R11_UND = INTREG_R11,
196 INTREG_R12_UND = INTREG_R12,
197 INTREG_PC_UND = INTREG_PC,
198
199 /* IRQ mode */
200 INTREG_R0_IRQ = INTREG_R0,
201 INTREG_R1_IRQ = INTREG_R1,
202 INTREG_R2_IRQ = INTREG_R2,
203 INTREG_R3_IRQ = INTREG_R3,
204 INTREG_R4_IRQ = INTREG_R4,
205 INTREG_R5_IRQ = INTREG_R5,
206 INTREG_R6_IRQ = INTREG_R6,
207 INTREG_R7_IRQ = INTREG_R7,
208 INTREG_R8_IRQ = INTREG_R8,
209 INTREG_R9_IRQ = INTREG_R9,
210 INTREG_R10_IRQ = INTREG_R10,
211 INTREG_R11_IRQ = INTREG_R11,
212 INTREG_R12_IRQ = INTREG_R12,
213 INTREG_PC_IRQ = INTREG_PC,
214
215 /* FIQ mode */
216 INTREG_R0_FIQ = INTREG_R0,
217 INTREG_R1_FIQ = INTREG_R1,
218 INTREG_R2_FIQ = INTREG_R2,
219 INTREG_R3_FIQ = INTREG_R3,
220 INTREG_R4_FIQ = INTREG_R4,
221 INTREG_R5_FIQ = INTREG_R5,
222 INTREG_R6_FIQ = INTREG_R6,
223 INTREG_R7_FIQ = INTREG_R7,
224 INTREG_PC_FIQ = INTREG_PC,
225};
226
227typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
228
229const IntRegMap IntRegUsrMap = {
230 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
231 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
232 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
233 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
234};
235
236static inline IntRegIndex
237INTREG_USR(unsigned index)
238{
239 assert(index < NUM_ARCH_INTREGS);
240 return IntRegUsrMap[index];
241}
242
243const IntRegMap IntRegSvcMap = {
244 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
245 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
246 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
247 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
248};
249
250static inline IntRegIndex
251INTREG_SVC(unsigned index)
252{
253 assert(index < NUM_ARCH_INTREGS);
254 return IntRegSvcMap[index];
255}
256
257const IntRegMap IntRegMonMap = {
258 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
259 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
260 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
261 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
262};
263
264static inline IntRegIndex
265INTREG_MON(unsigned index)
266{
267 assert(index < NUM_ARCH_INTREGS);
268 return IntRegMonMap[index];
269}
270
271const IntRegMap IntRegAbtMap = {
272 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
273 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
274 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
275 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
276};
277
278static inline IntRegIndex
279INTREG_ABT(unsigned index)
280{
281 assert(index < NUM_ARCH_INTREGS);
282 return IntRegAbtMap[index];
283}
284
285const IntRegMap IntRegUndMap = {
286 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
287 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
288 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
289 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
290};
291
292static inline IntRegIndex
293INTREG_UND(unsigned index)
294{
295 assert(index < NUM_ARCH_INTREGS);
296 return IntRegUndMap[index];
297}
298
299const IntRegMap IntRegIrqMap = {
300 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
301 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
302 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
303 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
304};
305
306static inline IntRegIndex
307INTREG_IRQ(unsigned index)
308{
309 assert(index < NUM_ARCH_INTREGS);
310 return IntRegIrqMap[index];
311}
312
313const IntRegMap IntRegFiqMap = {
314 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
315 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
316 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
317 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
318};
319
320static inline IntRegIndex
321INTREG_FIQ(unsigned index)
322{
323 assert(index < NUM_ARCH_INTREGS);
324 return IntRegFiqMap[index];
325}
326
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