1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include <assert.h>
32
33#ifndef __ARCH_ARM_INTREGS_HH__
34#define __ARCH_ARM_INTREGS_HH__
35
36namespace ArmISA
37{
38
39enum IntRegIndex
40{
41 /* All the unique register indices. */
42 INTREG_R0,
43 INTREG_R1,
44 INTREG_R2,
45 INTREG_R3,
46 INTREG_R4,
47 INTREG_R5,
48 INTREG_R6,
49 INTREG_R7,
50 INTREG_R8,
51 INTREG_R9,
52 INTREG_R10,
53 INTREG_R11,
54 INTREG_R12,
55 INTREG_R13,
56 INTREG_SP = INTREG_R13,
57 INTREG_R14,
58 INTREG_LR = INTREG_R14,
59 INTREG_R15,
60 INTREG_PC = INTREG_R15,
61
62 INTREG_R13_SVC,
63 INTREG_SP_SVC = INTREG_R13_SVC,
64 INTREG_R14_SVC,
65 INTREG_LR_SVC = INTREG_R14_SVC,
66 INTREG_R15_SVC = INTREG_R15,
67
68 INTREG_R13_MON,
69 INTREG_SP_MON = INTREG_R13_MON,
70 INTREG_R14_MON,
71 INTREG_LR_MON = INTREG_R14_MON,
72 INTREG_R15_MON = INTREG_R15,
73
74 INTREG_R13_ABT,
75 INTREG_SP_ABT = INTREG_R13_ABT,
76 INTREG_R14_ABT,
77 INTREG_LR_ABT = INTREG_R14_ABT,
78 INTREG_R15_ABT = INTREG_R15,
79
80 INTREG_R13_UND,
81 INTREG_SP_UND = INTREG_R13_UND,
82 INTREG_R14_UND,
83 INTREG_LR_UND = INTREG_R14_UND,
84 INTREG_R15_UND = INTREG_R15,
85
86 INTREG_R13_IRQ,
87 INTREG_SP_IRQ = INTREG_R13_IRQ,
88 INTREG_R14_IRQ,
89 INTREG_LR_IRQ = INTREG_R14_IRQ,
90 INTREG_R15_IRQ = INTREG_R15,
91
92 INTREG_R8_FIQ,
93 INTREG_R9_FIQ,
94 INTREG_R10_FIQ,
95 INTREG_R11_FIQ,
96 INTREG_R12_FIQ,
97 INTREG_R13_FIQ,
98 INTREG_SP_FIQ = INTREG_R13_FIQ,
99 INTREG_R14_FIQ,
100 INTREG_LR_FIQ = INTREG_R14_FIQ,
101 INTREG_R15_FIQ = INTREG_R15,
102
103 INTREG_ZERO, // Dummy zero reg since there has to be one.
104 INTREG_UREG0,
| 1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include <assert.h>
32
33#ifndef __ARCH_ARM_INTREGS_HH__
34#define __ARCH_ARM_INTREGS_HH__
35
36namespace ArmISA
37{
38
39enum IntRegIndex
40{
41 /* All the unique register indices. */
42 INTREG_R0,
43 INTREG_R1,
44 INTREG_R2,
45 INTREG_R3,
46 INTREG_R4,
47 INTREG_R5,
48 INTREG_R6,
49 INTREG_R7,
50 INTREG_R8,
51 INTREG_R9,
52 INTREG_R10,
53 INTREG_R11,
54 INTREG_R12,
55 INTREG_R13,
56 INTREG_SP = INTREG_R13,
57 INTREG_R14,
58 INTREG_LR = INTREG_R14,
59 INTREG_R15,
60 INTREG_PC = INTREG_R15,
61
62 INTREG_R13_SVC,
63 INTREG_SP_SVC = INTREG_R13_SVC,
64 INTREG_R14_SVC,
65 INTREG_LR_SVC = INTREG_R14_SVC,
66 INTREG_R15_SVC = INTREG_R15,
67
68 INTREG_R13_MON,
69 INTREG_SP_MON = INTREG_R13_MON,
70 INTREG_R14_MON,
71 INTREG_LR_MON = INTREG_R14_MON,
72 INTREG_R15_MON = INTREG_R15,
73
74 INTREG_R13_ABT,
75 INTREG_SP_ABT = INTREG_R13_ABT,
76 INTREG_R14_ABT,
77 INTREG_LR_ABT = INTREG_R14_ABT,
78 INTREG_R15_ABT = INTREG_R15,
79
80 INTREG_R13_UND,
81 INTREG_SP_UND = INTREG_R13_UND,
82 INTREG_R14_UND,
83 INTREG_LR_UND = INTREG_R14_UND,
84 INTREG_R15_UND = INTREG_R15,
85
86 INTREG_R13_IRQ,
87 INTREG_SP_IRQ = INTREG_R13_IRQ,
88 INTREG_R14_IRQ,
89 INTREG_LR_IRQ = INTREG_R14_IRQ,
90 INTREG_R15_IRQ = INTREG_R15,
91
92 INTREG_R8_FIQ,
93 INTREG_R9_FIQ,
94 INTREG_R10_FIQ,
95 INTREG_R11_FIQ,
96 INTREG_R12_FIQ,
97 INTREG_R13_FIQ,
98 INTREG_SP_FIQ = INTREG_R13_FIQ,
99 INTREG_R14_FIQ,
100 INTREG_LR_FIQ = INTREG_R14_FIQ,
101 INTREG_R15_FIQ = INTREG_R15,
102
103 INTREG_ZERO, // Dummy zero reg since there has to be one.
104 INTREG_UREG0,
|
105
106 NUM_INTREGS,
107 NUM_ARCH_INTREGS = INTREG_PC + 1,
108
109 /* All the aliased indexes. */
110
111 /* USR mode */
112 INTREG_R0_USR = INTREG_R0,
113 INTREG_R1_USR = INTREG_R1,
114 INTREG_R2_USR = INTREG_R2,
115 INTREG_R3_USR = INTREG_R3,
116 INTREG_R4_USR = INTREG_R4,
117 INTREG_R5_USR = INTREG_R5,
118 INTREG_R6_USR = INTREG_R6,
119 INTREG_R7_USR = INTREG_R7,
120 INTREG_R8_USR = INTREG_R8,
121 INTREG_R9_USR = INTREG_R9,
122 INTREG_R10_USR = INTREG_R10,
123 INTREG_R11_USR = INTREG_R11,
124 INTREG_R12_USR = INTREG_R12,
125 INTREG_R13_USR = INTREG_R13,
126 INTREG_SP_USR = INTREG_SP,
127 INTREG_R14_USR = INTREG_R14,
128 INTREG_LR_USR = INTREG_LR,
129 INTREG_R15_USR = INTREG_R15,
130 INTREG_PC_USR = INTREG_PC,
131
132 /* SVC mode */
133 INTREG_R0_SVC = INTREG_R0,
134 INTREG_R1_SVC = INTREG_R1,
135 INTREG_R2_SVC = INTREG_R2,
136 INTREG_R3_SVC = INTREG_R3,
137 INTREG_R4_SVC = INTREG_R4,
138 INTREG_R5_SVC = INTREG_R5,
139 INTREG_R6_SVC = INTREG_R6,
140 INTREG_R7_SVC = INTREG_R7,
141 INTREG_R8_SVC = INTREG_R8,
142 INTREG_R9_SVC = INTREG_R9,
143 INTREG_R10_SVC = INTREG_R10,
144 INTREG_R11_SVC = INTREG_R11,
145 INTREG_R12_SVC = INTREG_R12,
146 INTREG_PC_SVC = INTREG_PC,
147
148 /* MON mode */
149 INTREG_R0_MON = INTREG_R0,
150 INTREG_R1_MON = INTREG_R1,
151 INTREG_R2_MON = INTREG_R2,
152 INTREG_R3_MON = INTREG_R3,
153 INTREG_R4_MON = INTREG_R4,
154 INTREG_R5_MON = INTREG_R5,
155 INTREG_R6_MON = INTREG_R6,
156 INTREG_R7_MON = INTREG_R7,
157 INTREG_R8_MON = INTREG_R8,
158 INTREG_R9_MON = INTREG_R9,
159 INTREG_R10_MON = INTREG_R10,
160 INTREG_R11_MON = INTREG_R11,
161 INTREG_R12_MON = INTREG_R12,
162 INTREG_PC_MON = INTREG_PC,
163
164 /* ABT mode */
165 INTREG_R0_ABT = INTREG_R0,
166 INTREG_R1_ABT = INTREG_R1,
167 INTREG_R2_ABT = INTREG_R2,
168 INTREG_R3_ABT = INTREG_R3,
169 INTREG_R4_ABT = INTREG_R4,
170 INTREG_R5_ABT = INTREG_R5,
171 INTREG_R6_ABT = INTREG_R6,
172 INTREG_R7_ABT = INTREG_R7,
173 INTREG_R8_ABT = INTREG_R8,
174 INTREG_R9_ABT = INTREG_R9,
175 INTREG_R10_ABT = INTREG_R10,
176 INTREG_R11_ABT = INTREG_R11,
177 INTREG_R12_ABT = INTREG_R12,
178 INTREG_PC_ABT = INTREG_PC,
179
180 /* UND mode */
181 INTREG_R0_UND = INTREG_R0,
182 INTREG_R1_UND = INTREG_R1,
183 INTREG_R2_UND = INTREG_R2,
184 INTREG_R3_UND = INTREG_R3,
185 INTREG_R4_UND = INTREG_R4,
186 INTREG_R5_UND = INTREG_R5,
187 INTREG_R6_UND = INTREG_R6,
188 INTREG_R7_UND = INTREG_R7,
189 INTREG_R8_UND = INTREG_R8,
190 INTREG_R9_UND = INTREG_R9,
191 INTREG_R10_UND = INTREG_R10,
192 INTREG_R11_UND = INTREG_R11,
193 INTREG_R12_UND = INTREG_R12,
194 INTREG_PC_UND = INTREG_PC,
195
196 /* IRQ mode */
197 INTREG_R0_IRQ = INTREG_R0,
198 INTREG_R1_IRQ = INTREG_R1,
199 INTREG_R2_IRQ = INTREG_R2,
200 INTREG_R3_IRQ = INTREG_R3,
201 INTREG_R4_IRQ = INTREG_R4,
202 INTREG_R5_IRQ = INTREG_R5,
203 INTREG_R6_IRQ = INTREG_R6,
204 INTREG_R7_IRQ = INTREG_R7,
205 INTREG_R8_IRQ = INTREG_R8,
206 INTREG_R9_IRQ = INTREG_R9,
207 INTREG_R10_IRQ = INTREG_R10,
208 INTREG_R11_IRQ = INTREG_R11,
209 INTREG_R12_IRQ = INTREG_R12,
210 INTREG_PC_IRQ = INTREG_PC,
211
212 /* FIQ mode */
213 INTREG_R0_FIQ = INTREG_R0,
214 INTREG_R1_FIQ = INTREG_R1,
215 INTREG_R2_FIQ = INTREG_R2,
216 INTREG_R3_FIQ = INTREG_R3,
217 INTREG_R4_FIQ = INTREG_R4,
218 INTREG_R5_FIQ = INTREG_R5,
219 INTREG_R6_FIQ = INTREG_R6,
220 INTREG_R7_FIQ = INTREG_R7,
221 INTREG_PC_FIQ = INTREG_PC,
222};
223
224typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
225
226const IntRegMap IntRegUsrMap = {
227 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
228 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
229 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
230 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
231};
232
233static inline IntRegIndex
234INTREG_USR(unsigned index)
235{
236 assert(index < NUM_ARCH_INTREGS);
237 return IntRegUsrMap[index];
238}
239
240const IntRegMap IntRegSvcMap = {
241 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
242 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
243 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
244 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
245};
246
247static inline IntRegIndex
248INTREG_SVC(unsigned index)
249{
250 assert(index < NUM_ARCH_INTREGS);
251 return IntRegSvcMap[index];
252}
253
254const IntRegMap IntRegMonMap = {
255 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
256 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
257 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
258 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
259};
260
261static inline IntRegIndex
262INTREG_MON(unsigned index)
263{
264 assert(index < NUM_ARCH_INTREGS);
265 return IntRegMonMap[index];
266}
267
268const IntRegMap IntRegAbtMap = {
269 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
270 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
271 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
272 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
273};
274
275static inline IntRegIndex
276INTREG_ABT(unsigned index)
277{
278 assert(index < NUM_ARCH_INTREGS);
279 return IntRegAbtMap[index];
280}
281
282const IntRegMap IntRegUndMap = {
283 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
284 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
285 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
286 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
287};
288
289static inline IntRegIndex
290INTREG_UND(unsigned index)
291{
292 assert(index < NUM_ARCH_INTREGS);
293 return IntRegUndMap[index];
294}
295
296const IntRegMap IntRegIrqMap = {
297 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
298 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
299 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
300 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
301};
302
303static inline IntRegIndex
304INTREG_IRQ(unsigned index)
305{
306 assert(index < NUM_ARCH_INTREGS);
307 return IntRegIrqMap[index];
308}
309
310const IntRegMap IntRegFiqMap = {
311 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
312 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
313 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
314 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
315};
316
317static inline IntRegIndex
318INTREG_FIQ(unsigned index)
319{
320 assert(index < NUM_ARCH_INTREGS);
321 return IntRegFiqMap[index];
322}
323
324}
325
326#endif
| 107
108 NUM_INTREGS,
109 NUM_ARCH_INTREGS = INTREG_PC + 1,
110
111 /* All the aliased indexes. */
112
113 /* USR mode */
114 INTREG_R0_USR = INTREG_R0,
115 INTREG_R1_USR = INTREG_R1,
116 INTREG_R2_USR = INTREG_R2,
117 INTREG_R3_USR = INTREG_R3,
118 INTREG_R4_USR = INTREG_R4,
119 INTREG_R5_USR = INTREG_R5,
120 INTREG_R6_USR = INTREG_R6,
121 INTREG_R7_USR = INTREG_R7,
122 INTREG_R8_USR = INTREG_R8,
123 INTREG_R9_USR = INTREG_R9,
124 INTREG_R10_USR = INTREG_R10,
125 INTREG_R11_USR = INTREG_R11,
126 INTREG_R12_USR = INTREG_R12,
127 INTREG_R13_USR = INTREG_R13,
128 INTREG_SP_USR = INTREG_SP,
129 INTREG_R14_USR = INTREG_R14,
130 INTREG_LR_USR = INTREG_LR,
131 INTREG_R15_USR = INTREG_R15,
132 INTREG_PC_USR = INTREG_PC,
133
134 /* SVC mode */
135 INTREG_R0_SVC = INTREG_R0,
136 INTREG_R1_SVC = INTREG_R1,
137 INTREG_R2_SVC = INTREG_R2,
138 INTREG_R3_SVC = INTREG_R3,
139 INTREG_R4_SVC = INTREG_R4,
140 INTREG_R5_SVC = INTREG_R5,
141 INTREG_R6_SVC = INTREG_R6,
142 INTREG_R7_SVC = INTREG_R7,
143 INTREG_R8_SVC = INTREG_R8,
144 INTREG_R9_SVC = INTREG_R9,
145 INTREG_R10_SVC = INTREG_R10,
146 INTREG_R11_SVC = INTREG_R11,
147 INTREG_R12_SVC = INTREG_R12,
148 INTREG_PC_SVC = INTREG_PC,
149
150 /* MON mode */
151 INTREG_R0_MON = INTREG_R0,
152 INTREG_R1_MON = INTREG_R1,
153 INTREG_R2_MON = INTREG_R2,
154 INTREG_R3_MON = INTREG_R3,
155 INTREG_R4_MON = INTREG_R4,
156 INTREG_R5_MON = INTREG_R5,
157 INTREG_R6_MON = INTREG_R6,
158 INTREG_R7_MON = INTREG_R7,
159 INTREG_R8_MON = INTREG_R8,
160 INTREG_R9_MON = INTREG_R9,
161 INTREG_R10_MON = INTREG_R10,
162 INTREG_R11_MON = INTREG_R11,
163 INTREG_R12_MON = INTREG_R12,
164 INTREG_PC_MON = INTREG_PC,
165
166 /* ABT mode */
167 INTREG_R0_ABT = INTREG_R0,
168 INTREG_R1_ABT = INTREG_R1,
169 INTREG_R2_ABT = INTREG_R2,
170 INTREG_R3_ABT = INTREG_R3,
171 INTREG_R4_ABT = INTREG_R4,
172 INTREG_R5_ABT = INTREG_R5,
173 INTREG_R6_ABT = INTREG_R6,
174 INTREG_R7_ABT = INTREG_R7,
175 INTREG_R8_ABT = INTREG_R8,
176 INTREG_R9_ABT = INTREG_R9,
177 INTREG_R10_ABT = INTREG_R10,
178 INTREG_R11_ABT = INTREG_R11,
179 INTREG_R12_ABT = INTREG_R12,
180 INTREG_PC_ABT = INTREG_PC,
181
182 /* UND mode */
183 INTREG_R0_UND = INTREG_R0,
184 INTREG_R1_UND = INTREG_R1,
185 INTREG_R2_UND = INTREG_R2,
186 INTREG_R3_UND = INTREG_R3,
187 INTREG_R4_UND = INTREG_R4,
188 INTREG_R5_UND = INTREG_R5,
189 INTREG_R6_UND = INTREG_R6,
190 INTREG_R7_UND = INTREG_R7,
191 INTREG_R8_UND = INTREG_R8,
192 INTREG_R9_UND = INTREG_R9,
193 INTREG_R10_UND = INTREG_R10,
194 INTREG_R11_UND = INTREG_R11,
195 INTREG_R12_UND = INTREG_R12,
196 INTREG_PC_UND = INTREG_PC,
197
198 /* IRQ mode */
199 INTREG_R0_IRQ = INTREG_R0,
200 INTREG_R1_IRQ = INTREG_R1,
201 INTREG_R2_IRQ = INTREG_R2,
202 INTREG_R3_IRQ = INTREG_R3,
203 INTREG_R4_IRQ = INTREG_R4,
204 INTREG_R5_IRQ = INTREG_R5,
205 INTREG_R6_IRQ = INTREG_R6,
206 INTREG_R7_IRQ = INTREG_R7,
207 INTREG_R8_IRQ = INTREG_R8,
208 INTREG_R9_IRQ = INTREG_R9,
209 INTREG_R10_IRQ = INTREG_R10,
210 INTREG_R11_IRQ = INTREG_R11,
211 INTREG_R12_IRQ = INTREG_R12,
212 INTREG_PC_IRQ = INTREG_PC,
213
214 /* FIQ mode */
215 INTREG_R0_FIQ = INTREG_R0,
216 INTREG_R1_FIQ = INTREG_R1,
217 INTREG_R2_FIQ = INTREG_R2,
218 INTREG_R3_FIQ = INTREG_R3,
219 INTREG_R4_FIQ = INTREG_R4,
220 INTREG_R5_FIQ = INTREG_R5,
221 INTREG_R6_FIQ = INTREG_R6,
222 INTREG_R7_FIQ = INTREG_R7,
223 INTREG_PC_FIQ = INTREG_PC,
224};
225
226typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
227
228const IntRegMap IntRegUsrMap = {
229 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
230 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
231 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
232 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
233};
234
235static inline IntRegIndex
236INTREG_USR(unsigned index)
237{
238 assert(index < NUM_ARCH_INTREGS);
239 return IntRegUsrMap[index];
240}
241
242const IntRegMap IntRegSvcMap = {
243 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
244 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
245 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
246 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
247};
248
249static inline IntRegIndex
250INTREG_SVC(unsigned index)
251{
252 assert(index < NUM_ARCH_INTREGS);
253 return IntRegSvcMap[index];
254}
255
256const IntRegMap IntRegMonMap = {
257 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
258 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
259 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
260 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
261};
262
263static inline IntRegIndex
264INTREG_MON(unsigned index)
265{
266 assert(index < NUM_ARCH_INTREGS);
267 return IntRegMonMap[index];
268}
269
270const IntRegMap IntRegAbtMap = {
271 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
272 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
273 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
274 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
275};
276
277static inline IntRegIndex
278INTREG_ABT(unsigned index)
279{
280 assert(index < NUM_ARCH_INTREGS);
281 return IntRegAbtMap[index];
282}
283
284const IntRegMap IntRegUndMap = {
285 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
286 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
287 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
288 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
289};
290
291static inline IntRegIndex
292INTREG_UND(unsigned index)
293{
294 assert(index < NUM_ARCH_INTREGS);
295 return IntRegUndMap[index];
296}
297
298const IntRegMap IntRegIrqMap = {
299 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
300 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
301 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
302 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
303};
304
305static inline IntRegIndex
306INTREG_IRQ(unsigned index)
307{
308 assert(index < NUM_ARCH_INTREGS);
309 return IntRegIrqMap[index];
310}
311
312const IntRegMap IntRegFiqMap = {
313 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
314 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
315 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
316 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
317};
318
319static inline IntRegIndex
320INTREG_FIQ(unsigned index)
321{
322 assert(index < NUM_ARCH_INTREGS);
323 return IntRegFiqMap[index];
324}
325
326}
327
328#endif
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