1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include <cassert>
44
45#ifndef __ARCH_ARM_INTREGS_HH__
46#define __ARCH_ARM_INTREGS_HH__
47
48#include "arch/arm/types.hh"
49
50namespace ArmISA
51{
52
53enum IntRegIndex
54{
55 /* All the unique register indices. */
56 INTREG_R0,
57 INTREG_R1,
58 INTREG_R2,
59 INTREG_R3,
60 INTREG_R4,
61 INTREG_R5,
62 INTREG_R6,
63 INTREG_R7,
64 INTREG_R8,
65 INTREG_R9,
66 INTREG_R10,
67 INTREG_R11,
68 INTREG_R12,
69 INTREG_R13,
70 INTREG_SP = INTREG_R13,
71 INTREG_R14,
72 INTREG_LR = INTREG_R14,
73 INTREG_R15,
74 INTREG_PC = INTREG_R15,
75
76 INTREG_R13_SVC,
77 INTREG_SP_SVC = INTREG_R13_SVC,
78 INTREG_R14_SVC,
79 INTREG_LR_SVC = INTREG_R14_SVC,
80
81 INTREG_R13_MON,
82 INTREG_SP_MON = INTREG_R13_MON,
83 INTREG_R14_MON,
84 INTREG_LR_MON = INTREG_R14_MON,
85
86 INTREG_R13_HYP,
87 INTREG_SP_HYP = INTREG_R13_HYP,
88
89 INTREG_R13_ABT,
90 INTREG_SP_ABT = INTREG_R13_ABT,
91 INTREG_R14_ABT,
92 INTREG_LR_ABT = INTREG_R14_ABT,
93
94 INTREG_R13_UND,
95 INTREG_SP_UND = INTREG_R13_UND,
96 INTREG_R14_UND,
97 INTREG_LR_UND = INTREG_R14_UND,
98
99 INTREG_R13_IRQ,
100 INTREG_SP_IRQ = INTREG_R13_IRQ,
101 INTREG_R14_IRQ,
102 INTREG_LR_IRQ = INTREG_R14_IRQ,
103
104 INTREG_R8_FIQ,
105 INTREG_R9_FIQ,
106 INTREG_R10_FIQ,
107 INTREG_R11_FIQ,
108 INTREG_R12_FIQ,
109 INTREG_R13_FIQ,
110 INTREG_SP_FIQ = INTREG_R13_FIQ,
111 INTREG_R14_FIQ,
112 INTREG_LR_FIQ = INTREG_R14_FIQ,
113
114 INTREG_ZERO,
115 INTREG_UREG0,
116 INTREG_UREG1,
117 INTREG_UREG2,
118 INTREG_CONDCODES_NZ,
119 INTREG_CONDCODES_C,
120 INTREG_CONDCODES_V,
121 INTREG_CONDCODES_GE,
122 INTREG_FPCONDCODES,
123 INTREG_DUMMY, // Dummy reg used to throw away int reg results
124
125 INTREG_SP0,
126 INTREG_SP1,
127 INTREG_SP2,
128 INTREG_SP3,
129
130 NUM_INTREGS,
131 NUM_ARCH_INTREGS = 32,
132
133 /* AArch64 registers */
134 INTREG_X0 = 0,
135 INTREG_X1,
136 INTREG_X2,
137 INTREG_X3,
138 INTREG_X4,
139 INTREG_X5,
140 INTREG_X6,
141 INTREG_X7,
142 INTREG_X8,
143 INTREG_X9,
144 INTREG_X10,
145 INTREG_X11,
146 INTREG_X12,
147 INTREG_X13,
148 INTREG_X14,
149 INTREG_X15,
150 INTREG_X16,
151 INTREG_X17,
152 INTREG_X18,
153 INTREG_X19,
154 INTREG_X20,
155 INTREG_X21,
156 INTREG_X22,
157 INTREG_X23,
158 INTREG_X24,
159 INTREG_X25,
160 INTREG_X26,
161 INTREG_X27,
162 INTREG_X28,
163 INTREG_X29,
164 INTREG_X30,
165 INTREG_X31,
166
167 INTREG_SPX = NUM_INTREGS,
168
169 /* All the aliased indexes. */
170
171 /* USR mode */
172 INTREG_R0_USR = INTREG_R0,
173 INTREG_R1_USR = INTREG_R1,
174 INTREG_R2_USR = INTREG_R2,
175 INTREG_R3_USR = INTREG_R3,
176 INTREG_R4_USR = INTREG_R4,
177 INTREG_R5_USR = INTREG_R5,
178 INTREG_R6_USR = INTREG_R6,
179 INTREG_R7_USR = INTREG_R7,
180 INTREG_R8_USR = INTREG_R8,
181 INTREG_R9_USR = INTREG_R9,
182 INTREG_R10_USR = INTREG_R10,
183 INTREG_R11_USR = INTREG_R11,
184 INTREG_R12_USR = INTREG_R12,
185 INTREG_R13_USR = INTREG_R13,
186 INTREG_SP_USR = INTREG_SP,
187 INTREG_R14_USR = INTREG_R14,
188 INTREG_LR_USR = INTREG_LR,
189 INTREG_R15_USR = INTREG_R15,
190 INTREG_PC_USR = INTREG_PC,
191
192 /* SVC mode */
193 INTREG_R0_SVC = INTREG_R0,
194 INTREG_R1_SVC = INTREG_R1,
195 INTREG_R2_SVC = INTREG_R2,
196 INTREG_R3_SVC = INTREG_R3,
197 INTREG_R4_SVC = INTREG_R4,
198 INTREG_R5_SVC = INTREG_R5,
199 INTREG_R6_SVC = INTREG_R6,
200 INTREG_R7_SVC = INTREG_R7,
201 INTREG_R8_SVC = INTREG_R8,
202 INTREG_R9_SVC = INTREG_R9,
203 INTREG_R10_SVC = INTREG_R10,
204 INTREG_R11_SVC = INTREG_R11,
205 INTREG_R12_SVC = INTREG_R12,
206 INTREG_PC_SVC = INTREG_PC,
207 INTREG_R15_SVC = INTREG_R15,
208
209 /* MON mode */
210 INTREG_R0_MON = INTREG_R0,
211 INTREG_R1_MON = INTREG_R1,
212 INTREG_R2_MON = INTREG_R2,
213 INTREG_R3_MON = INTREG_R3,
214 INTREG_R4_MON = INTREG_R4,
215 INTREG_R5_MON = INTREG_R5,
216 INTREG_R6_MON = INTREG_R6,
217 INTREG_R7_MON = INTREG_R7,
218 INTREG_R8_MON = INTREG_R8,
219 INTREG_R9_MON = INTREG_R9,
220 INTREG_R10_MON = INTREG_R10,
221 INTREG_R11_MON = INTREG_R11,
222 INTREG_R12_MON = INTREG_R12,
223 INTREG_PC_MON = INTREG_PC,
224 INTREG_R15_MON = INTREG_R15,
225
226 /* ABT mode */
227 INTREG_R0_ABT = INTREG_R0,
228 INTREG_R1_ABT = INTREG_R1,
229 INTREG_R2_ABT = INTREG_R2,
230 INTREG_R3_ABT = INTREG_R3,
231 INTREG_R4_ABT = INTREG_R4,
232 INTREG_R5_ABT = INTREG_R5,
233 INTREG_R6_ABT = INTREG_R6,
234 INTREG_R7_ABT = INTREG_R7,
235 INTREG_R8_ABT = INTREG_R8,
236 INTREG_R9_ABT = INTREG_R9,
237 INTREG_R10_ABT = INTREG_R10,
238 INTREG_R11_ABT = INTREG_R11,
239 INTREG_R12_ABT = INTREG_R12,
240 INTREG_PC_ABT = INTREG_PC,
241 INTREG_R15_ABT = INTREG_R15,
242
243 /* HYP mode */
244 INTREG_R0_HYP = INTREG_R0,
245 INTREG_R1_HYP = INTREG_R1,
246 INTREG_R2_HYP = INTREG_R2,
247 INTREG_R3_HYP = INTREG_R3,
248 INTREG_R4_HYP = INTREG_R4,
249 INTREG_R5_HYP = INTREG_R5,
250 INTREG_R6_HYP = INTREG_R6,
251 INTREG_R7_HYP = INTREG_R7,
252 INTREG_R8_HYP = INTREG_R8,
253 INTREG_R9_HYP = INTREG_R9,
254 INTREG_R10_HYP = INTREG_R10,
255 INTREG_R11_HYP = INTREG_R11,
256 INTREG_R12_HYP = INTREG_R12,
257 INTREG_LR_HYP = INTREG_LR,
258 INTREG_R14_HYP = INTREG_R14,
259 INTREG_PC_HYP = INTREG_PC,
260 INTREG_R15_HYP = INTREG_R15,
261
262 /* UND mode */
263 INTREG_R0_UND = INTREG_R0,
264 INTREG_R1_UND = INTREG_R1,
265 INTREG_R2_UND = INTREG_R2,
266 INTREG_R3_UND = INTREG_R3,
267 INTREG_R4_UND = INTREG_R4,
268 INTREG_R5_UND = INTREG_R5,
269 INTREG_R6_UND = INTREG_R6,
270 INTREG_R7_UND = INTREG_R7,
271 INTREG_R8_UND = INTREG_R8,
272 INTREG_R9_UND = INTREG_R9,
273 INTREG_R10_UND = INTREG_R10,
274 INTREG_R11_UND = INTREG_R11,
275 INTREG_R12_UND = INTREG_R12,
276 INTREG_PC_UND = INTREG_PC,
277 INTREG_R15_UND = INTREG_R15,
278
279 /* IRQ mode */
280 INTREG_R0_IRQ = INTREG_R0,
281 INTREG_R1_IRQ = INTREG_R1,
282 INTREG_R2_IRQ = INTREG_R2,
283 INTREG_R3_IRQ = INTREG_R3,
284 INTREG_R4_IRQ = INTREG_R4,
285 INTREG_R5_IRQ = INTREG_R5,
286 INTREG_R6_IRQ = INTREG_R6,
287 INTREG_R7_IRQ = INTREG_R7,
288 INTREG_R8_IRQ = INTREG_R8,
289 INTREG_R9_IRQ = INTREG_R9,
290 INTREG_R10_IRQ = INTREG_R10,
291 INTREG_R11_IRQ = INTREG_R11,
292 INTREG_R12_IRQ = INTREG_R12,
293 INTREG_PC_IRQ = INTREG_PC,
294 INTREG_R15_IRQ = INTREG_R15,
295
296 /* FIQ mode */
297 INTREG_R0_FIQ = INTREG_R0,
298 INTREG_R1_FIQ = INTREG_R1,
299 INTREG_R2_FIQ = INTREG_R2,
300 INTREG_R3_FIQ = INTREG_R3,
301 INTREG_R4_FIQ = INTREG_R4,
302 INTREG_R5_FIQ = INTREG_R5,
303 INTREG_R6_FIQ = INTREG_R6,
304 INTREG_R7_FIQ = INTREG_R7,
305 INTREG_PC_FIQ = INTREG_PC,
306 INTREG_R15_FIQ = INTREG_R15
307};
308
309typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
310
311const IntRegMap IntReg64Map = {
312 INTREG_R0, INTREG_R1, INTREG_R2, INTREG_R3,
313 INTREG_R4, INTREG_R5, INTREG_R6, INTREG_R7,
314 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
315 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
316 INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
317 INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
318 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
319 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
320};
321
322const IntRegMap IntRegUsrMap = {
323 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
324 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
325 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
326 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
327 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
328 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
329 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
330 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
331};
332
333static inline IntRegIndex
334INTREG_USR(unsigned index)
335{
336 assert(index < NUM_ARCH_INTREGS);
337 return IntRegUsrMap[index];
338}
339
340const IntRegMap IntRegHypMap = {
341 INTREG_R0_HYP, INTREG_R1_HYP, INTREG_R2_HYP, INTREG_R3_HYP,
342 INTREG_R4_HYP, INTREG_R5_HYP, INTREG_R6_HYP, INTREG_R7_HYP,
343 INTREG_R8_HYP, INTREG_R9_HYP, INTREG_R10_HYP, INTREG_R11_HYP,
344 INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
345 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
346 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
347 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
348 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
349};
350
351static inline IntRegIndex
352INTREG_HYP(unsigned index)
353{
354 assert(index < NUM_ARCH_INTREGS);
355 return IntRegHypMap[index];
356}
357
358const IntRegMap IntRegSvcMap = {
359 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
360 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
361 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
362 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
363 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
364 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
365 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
366 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
367};
368
369static inline IntRegIndex
370INTREG_SVC(unsigned index)
371{
372 assert(index < NUM_ARCH_INTREGS);
373 return IntRegSvcMap[index];
374}
375
376const IntRegMap IntRegMonMap = {
377 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
378 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
379 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
380 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
381 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
382 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
383 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
384 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
385};
386
387static inline IntRegIndex
388INTREG_MON(unsigned index)
389{
390 assert(index < NUM_ARCH_INTREGS);
391 return IntRegMonMap[index];
392}
393
394const IntRegMap IntRegAbtMap = {
395 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
396 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
397 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
398 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
399 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
400 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
401 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
402 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
403};
404
405static inline IntRegIndex
406INTREG_ABT(unsigned index)
407{
408 assert(index < NUM_ARCH_INTREGS);
409 return IntRegAbtMap[index];
410}
411
412const IntRegMap IntRegUndMap = {
413 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
414 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
415 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
416 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
417 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
418 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
419 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
420 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
421};
422
423static inline IntRegIndex
424INTREG_UND(unsigned index)
425{
426 assert(index < NUM_ARCH_INTREGS);
427 return IntRegUndMap[index];
428}
429
430const IntRegMap IntRegIrqMap = {
431 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
432 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
433 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
434 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
435 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
436 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
437 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
438 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
439};
440
441static inline IntRegIndex
442INTREG_IRQ(unsigned index)
443{
444 assert(index < NUM_ARCH_INTREGS);
445 return IntRegIrqMap[index];
446}
447
448const IntRegMap IntRegFiqMap = {
449 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
450 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
451 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
452 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
453 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
454 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
455 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
456 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
457};
458
459static inline IntRegIndex
460INTREG_FIQ(unsigned index)
461{
462 assert(index < NUM_ARCH_INTREGS);
463 return IntRegFiqMap[index];
464}
465
466static const unsigned intRegsPerMode = NUM_INTREGS;
467
468static inline int
469intRegInMode(OperatingMode mode, int reg)
470{
471 assert(reg < NUM_ARCH_INTREGS);
472 return mode * intRegsPerMode + reg;
473}
474
475static inline int
476flattenIntRegModeIndex(int reg)
477{
478 int mode = reg / intRegsPerMode;
479 reg = reg % intRegsPerMode;
480 switch (mode) {
481 case MODE_USER:
482 case MODE_SYSTEM:
483 return INTREG_USR(reg);
484 case MODE_FIQ:
485 return INTREG_FIQ(reg);
486 case MODE_IRQ:
487 return INTREG_IRQ(reg);
488 case MODE_SVC:
489 return INTREG_SVC(reg);
490 case MODE_MON:
491 return INTREG_MON(reg);
492 case MODE_ABORT:
493 return INTREG_ABT(reg);
494 case MODE_HYP:
495 return INTREG_HYP(reg);
496 case MODE_UNDEFINED:
497 return INTREG_UND(reg);
498 default:
499 panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
500 curTick(), reg, mode);
501 }
502}
503
504
505static inline IntRegIndex
506makeSP(IntRegIndex reg)
507{
508 if (reg == INTREG_X31)
509 reg = INTREG_SPX;
510 return reg;
511}
512
513static inline IntRegIndex
514makeZero(IntRegIndex reg)
515{
516 if (reg == INTREG_X31)
517 reg = INTREG_ZERO;
518 return reg;
519}
520
521static inline bool
522isSP(IntRegIndex reg)
523{
524 return reg == INTREG_SPX;
525}
526
527}
528
529#endif