1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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40 * Authors: Gabe Black
41 */
42
43#include <assert.h>
44
45#ifndef __ARCH_ARM_INTREGS_HH__
46#define __ARCH_ARM_INTREGS_HH__
47
48#include "arch/arm/types.hh"
49
50namespace ArmISA
51{
52
53enum IntRegIndex
54{
55 /* All the unique register indices. */
56 INTREG_R0,
57 INTREG_R1,

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331
332static inline IntRegIndex
333INTREG_FIQ(unsigned index)
334{
335 assert(index < NUM_ARCH_INTREGS);
336 return IntRegFiqMap[index];
337}
338
339static const unsigned intRegsPerMode = NUM_INTREGS;
340
341static inline int
342intRegInMode(OperatingMode mode, int reg)
343{
344 assert(reg < NUM_ARCH_INTREGS);
345 return mode * intRegsPerMode + reg;
346}
347
348}
349
350#endif