misc64.cc (14127:65faf17eea53) misc64.cc (14128:6ed23d07d0d1)
1/*
2 * Copyright (c) 2011-2013,2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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322 return trap_to_mon;
323}
324
325RegVal
326MiscRegImmOp64::miscRegImm() const
327{
328 if (dest == MISCREG_SPSEL) {
329 return imm & 0x1;
1/*
2 * Copyright (c) 2011-2013,2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 313 unchanged lines hidden (view full) ---

322 return trap_to_mon;
323}
324
325RegVal
326MiscRegImmOp64::miscRegImm() const
327{
328 if (dest == MISCREG_SPSEL) {
329 return imm & 0x1;
330 } else if (dest == MISCREG_PAN) {
331 return (imm & 0x1) << 22;
330 } else {
331 panic("Not a valid PSTATE field register\n");
332 }
333}
334
335std::string
336MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
337{

--- 61 unchanged lines hidden --- 		332 } else {
333 panic("Not a valid PSTATE field register\n");
334 }
335}
336
337std::string
338MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
339{

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