misc64.cc (13895:5762b3dc79c6) misc64.cc (14001:11216534c23e)
1/*
1/*
2 * Copyright (c) 2011-2013,2017-2018 ARM Limited
2 * Copyright (c) 2011-2013,2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/misc64.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/misc64.hh"
41#include "arch/arm/isa.hh"
41
42std::string
43ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
44{
45 std::stringstream ss;
46 printMnemonic(ss, "", false);
47 ccprintf(ss, "#0x%x", imm);
48 return ss.str();

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263 // ID regs, group 1
264 case MISCREG_AIDR_EL1:
265 case MISCREG_REVIDR_EL1:
266 assert(miscRead);
267 trap_to_hyp = hcr.tid1 && el == EL1;
268 break;
269 case MISCREG_IMPDEF_UNIMPL:
270 trap_to_hyp = hcr.tidcp && el == EL1;
42
43std::string
44ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
45{
46 std::stringstream ss;
47 printMnemonic(ss, "", false);
48 ccprintf(ss, "#0x%x", imm);
49 return ss.str();

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264 // ID regs, group 1
265 case MISCREG_AIDR_EL1:
266 case MISCREG_REVIDR_EL1:
267 assert(miscRead);
268 trap_to_hyp = hcr.tid1 && el == EL1;
269 break;
270 case MISCREG_IMPDEF_UNIMPL:
271 trap_to_hyp = hcr.tidcp && el == EL1;
272 // GICv3 regs
273 case MISCREG_ICC_SGI0R_EL1:
274 if (tc->getIsaPtr()->haveGICv3CpuIfc())
275 trap_to_hyp = hcr.fmo && el == EL1;
276 break;
277 case MISCREG_ICC_SGI1R_EL1:
278 case MISCREG_ICC_ASGI1R_EL1:
279 if (tc->getIsaPtr()->haveGICv3CpuIfc())
280 trap_to_hyp = hcr.imo && el == EL1;
281 break;
271 default:
272 break;
273 }
274 }
275 return trap_to_hyp;
276}
277
278bool

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283 break;
284 }
285 }
286 return trap_to_hyp;
287}
288
289bool

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