misc64.cc (12104:edd63f9c6184) | misc64.cc (12280:a44a2326a02b) |
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1/* | 1/* |
2 * Copyright (c) 2011-2013 ARM Limited | 2 * Copyright (c) 2011-2013,2017 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 37 unchanged lines hidden (view full) --- 48 ss << ", "; 49 printIntReg(ss, op1); 50 ccprintf(ss, ", #%d, #%d", imm1, imm2); 51 return ss.str(); 52} 53 54std::string 55RegRegRegImmOp64::generateDisassembly( | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 37 unchanged lines hidden (view full) --- 48 ss << ", "; 49 printIntReg(ss, op1); 50 ccprintf(ss, ", #%d, #%d", imm1, imm2); 51 return ss.str(); 52} 53 54std::string 55RegRegRegImmOp64::generateDisassembly( |
56 Addr pc, const SymbolTable *symtab) const | 56 Addr pc, const SymbolTable *symtab) const |
57{ 58 std::stringstream ss; 59 printMnemonic(ss, "", false); 60 printIntReg(ss, dest); 61 ss << ", "; 62 printIntReg(ss, op1); 63 ss << ", "; 64 printIntReg(ss, op2); 65 ccprintf(ss, ", #%d", imm); 66 return ss.str(); 67} 68 69std::string 70UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 71{ 72 return csprintf("%-10s (inst %#08x)", "unknown", machInst); 73} | 57{ 58 std::stringstream ss; 59 printMnemonic(ss, "", false); 60 printIntReg(ss, dest); 61 ss << ", "; 62 printIntReg(ss, op1); 63 ss << ", "; 64 printIntReg(ss, op2); 65 ccprintf(ss, ", #%d", imm); 66 return ss.str(); 67} 68 69std::string 70UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 71{ 72 return csprintf("%-10s (inst %#08x)", "unknown", machInst); 73} |
74 75std::string 76MiscRegRegImmOp64::generateDisassembly( 77 Addr pc, const SymbolTable *symtab) const 78{ 79 std::stringstream ss; 80 printMnemonic(ss); 81 printMiscReg(ss, dest); 82 ss << ", "; 83 printIntReg(ss, op1); 84 return ss.str(); 85} 86 87std::string 88RegMiscRegImmOp64::generateDisassembly( 89 Addr pc, const SymbolTable *symtab) const 90{ 91 std::stringstream ss; 92 printMnemonic(ss); 93 printIntReg(ss, dest); 94 ss << ", "; 95 printMiscReg(ss, op1); 96 return ss.str(); 97} |
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