3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/misc64.hh"
41
42std::string
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/misc64.hh"
41
42std::string
|
43RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
44{
45 std::stringstream ss;
46 printMnemonic(ss, "", false);
47 printIntReg(ss, dest);
48 ss << ", ";
49 printIntReg(ss, op1);
50 ccprintf(ss, ", #%d, #%d", imm1, imm2);
51 return ss.str();
52}
53
54std::string
55RegRegRegImmOp64::generateDisassembly(
56 Addr pc, const SymbolTable *symtab) const
57{
58 std::stringstream ss;
59 printMnemonic(ss, "", false);
60 printIntReg(ss, dest);
61 ss << ", ";
62 printIntReg(ss, op1);
63 ss << ", ";
64 printIntReg(ss, op2);
65 ccprintf(ss, ", #%d", imm);
66 return ss.str();
67}
68
69std::string
70UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
71{
72 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
73}
74
75std::string
76MiscRegRegImmOp64::generateDisassembly(
77 Addr pc, const SymbolTable *symtab) const
78{
79 std::stringstream ss;
80 printMnemonic(ss);
81 printMiscReg(ss, dest);
82 ss << ", ";
83 printIntReg(ss, op1);
84 return ss.str();
85}
86
87std::string
88RegMiscRegImmOp64::generateDisassembly(
89 Addr pc, const SymbolTable *symtab) const
90{
91 std::stringstream ss;
92 printMnemonic(ss);
93 printIntReg(ss, dest);
94 ss << ", ";
95 printMiscReg(ss, op1);
96 return ss.str();
97}
| 52RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
53{
54 std::stringstream ss;
55 printMnemonic(ss, "", false);
56 printIntReg(ss, dest);
57 ss << ", ";
58 printIntReg(ss, op1);
59 ccprintf(ss, ", #%d, #%d", imm1, imm2);
60 return ss.str();
61}
62
63std::string
64RegRegRegImmOp64::generateDisassembly(
65 Addr pc, const SymbolTable *symtab) const
66{
67 std::stringstream ss;
68 printMnemonic(ss, "", false);
69 printIntReg(ss, dest);
70 ss << ", ";
71 printIntReg(ss, op1);
72 ss << ", ";
73 printIntReg(ss, op2);
74 ccprintf(ss, ", #%d", imm);
75 return ss.str();
76}
77
78std::string
79UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
80{
81 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
82}
83
84std::string
85MiscRegRegImmOp64::generateDisassembly(
86 Addr pc, const SymbolTable *symtab) const
87{
88 std::stringstream ss;
89 printMnemonic(ss);
90 printMiscReg(ss, dest);
91 ss << ", ";
92 printIntReg(ss, op1);
93 return ss.str();
94}
95
96std::string
97RegMiscRegImmOp64::generateDisassembly(
98 Addr pc, const SymbolTable *symtab) const
99{
100 std::stringstream ss;
101 printMnemonic(ss);
102 printIntReg(ss, dest);
103 ss << ", ";
104 printMiscReg(ss, op1);
105 return ss.str();
106}
|