1/*
2 * Copyright (c) 2011-2013,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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76}
77
78std::string
79UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
80{
81 return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32));
82}
83
84std::string
85MiscRegRegImmOp64::generateDisassembly(
86 Addr pc, const SymbolTable *symtab) const
87{
88 std::stringstream ss;
89 printMnemonic(ss);
90 printMiscReg(ss, dest);
91 ss << ", ";

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