misc.cc (7225:bf41a07cc7c0) misc.cc (7232:f633e1a3f644)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 141 unchanged lines hidden (view full) ---

150 printMnemonic(ss);
151 printReg(ss, dest);
152 ss << ", ";
153 printReg(ss, op1);
154 return ss.str();
155}
156
157std::string
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 141 unchanged lines hidden (view full) ---

150 printMnemonic(ss);
151 printReg(ss, dest);
152 ss << ", ";
153 printReg(ss, op1);
154 return ss.str();
155}
156
157std::string
158SatOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
158RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
159{
160 std::stringstream ss;
161 printMnemonic(ss);
162 printReg(ss, dest);
159{
160 std::stringstream ss;
161 printMnemonic(ss);
162 printReg(ss, dest);
163 ccprintf(ss, ", #%d, ", satImm);
163 ccprintf(ss, ", #%d, ", imm);
164 printReg(ss, op1);
165 return ss.str();
166}
167
168std::string
164 printReg(ss, op1);
165 return ss.str();
166}
167
168std::string
169SatShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
169RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
170{
171 std::stringstream ss;
172 printMnemonic(ss);
173 printReg(ss, dest);
170{
171 std::stringstream ss;
172 printMnemonic(ss);
173 printReg(ss, dest);
174 ccprintf(ss, ", #%d, ", satImm);
174 ccprintf(ss, ", #%d, ", imm);
175 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
176 printReg(ss, op1);
177 return ss.str();
178}
175 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
176 printReg(ss, op1);
177 return ss.str();
178}