misc.cc (13895:5762b3dc79c6) misc.cc (13999:a26c2e234a80)
1/*
2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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334 flags[IsNonSpeculative] = true;
335 iss = _iss;
336 miscReg = _miscReg;
337}
338
339Fault
340McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
341{
1/*
2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 325 unchanged lines hidden (view full) ---

334 flags[IsNonSpeculative] = true;
335 iss = _iss;
336 miscReg = _miscReg;
337}
338
339Fault
340McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
341{
342 uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
343 uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
344 uint32_t scr = xc->readMiscReg(MISCREG_SCR);
345 uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
346 uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
347 uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
342 bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
348
343
349 bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
350 hcptr, iss);
351 if (hypTrap) {
352 return std::make_shared<HypervisorTrap>(machInst, iss,
353 EC_TRAPPED_CP15_MCR_MRC);
354 } else {
355 return NoFault;
356 }
357}
358

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366 ExtMachInst _machInst, uint64_t _iss,
367 MiscRegIndex _miscReg)
368 : McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg)
369{}
370
371Fault
372McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
373{
344 if (hypTrap) {
345 return std::make_shared<HypervisorTrap>(machInst, iss,
346 EC_TRAPPED_CP15_MCR_MRC);
347 } else {
348 return NoFault;
349 }
350}
351

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359 ExtMachInst _machInst, uint64_t _iss,
360 MiscRegIndex _miscReg)
361 : McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg)
362{}
363
364Fault
365McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
366{
374 uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
375 uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
376 uint32_t scr = xc->readMiscReg(MISCREG_SCR);
377 uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
378 uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
379 uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
367 bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
380
368
381 bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
382 hcptr, iss);
383 if (hypTrap) {
384 return std::make_shared<HypervisorTrap>(machInst, iss,
385 EC_TRAPPED_CP15_MCR_MRC);
386 } else {
387 return std::make_shared<UndefinedInstruction>(machInst, false,
388 mnemonic);
389 }
390}
391
392std::string
393McrMrcImplDefined::generateDisassembly(Addr pc,
394 const SymbolTable *symtab) const
395{
396 return csprintf("%-10s (implementation defined)", mnemonic);
397}
369 if (hypTrap) {
370 return std::make_shared<HypervisorTrap>(machInst, iss,
371 EC_TRAPPED_CP15_MCR_MRC);
372 } else {
373 return std::make_shared<UndefinedInstruction>(machInst, false,
374 mnemonic);
375 }
376}
377
378std::string
379McrMrcImplDefined::generateDisassembly(Addr pc,
380 const SymbolTable *symtab) const
381{
382 return csprintf("%-10s (implementation defined)", mnemonic);
383}