misc.cc (13574:bab20b8d882d) misc.cc (13895:5762b3dc79c6)
1/*
2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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319 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
320 printIntReg(ss, op1);
321 return ss.str();
322}
323
324std::string
325UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
326{
1/*
2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 310 unchanged lines hidden (view full) ---

319 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
320 printIntReg(ss, op1);
321 return ss.str();
322}
323
324std::string
325UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
326{
327 return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32));
327 return csprintf("%-10s (inst %#08x)", "unknown", encoding());
328}
329
330McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
331 uint64_t _iss, MiscRegIndex _miscReg)
332 : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
333{
334 flags[IsNonSpeculative] = true;
335 iss = _iss;

--- 62 unchanged lines hidden --- 		328}
329
330McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
331 uint64_t _iss, MiscRegIndex _miscReg)
332 : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
333{
334 flags[IsNonSpeculative] = true;
335 iss = _iss;

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