misc.cc (12281:90315832cb81) misc.cc (12358:386d26feb00f)
1/*
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
2 * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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317 printIntReg(ss, dest);
318 ccprintf(ss, ", #%d, ", imm);
319 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
320 printIntReg(ss, op1);
321 return ss.str();
322}
323
324std::string
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

--- 306 unchanged lines hidden (view full) ---

317 printIntReg(ss, dest);
318 ccprintf(ss, ", #%d, ", imm);
319 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
320 printIntReg(ss, op1);
321 return ss.str();
322}
323
324std::string
325MiscRegRegImmMemOp::generateDisassembly(Addr pc,
326 const SymbolTable *symtab) const
327{
328 std::stringstream ss;
329 printMnemonic(ss);
330 printIntReg(ss, op1);
331 return ss.str();
332}
333
334std::string
325UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
326{
327 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
328}
335UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
336{
337 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
338}