50c50
< printReg(ss, dest);
---
> printIntReg(ss, dest);
54,56c54,55
< RegIndex idx = srcRegIdx(i);
< RegIndex rel_idx;
< if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
---
> RegId reg = srcRegIdx(i);
> if (reg.regClass != MiscRegClass) {
59c58
< if (rel_idx == MISCREG_CPSR) {
---
> if (reg.regIdx == MISCREG_CPSR) {
64c63
< if (rel_idx == MISCREG_SPSR) {
---
> if (reg.regIdx == MISCREG_SPSR) {
83,84c82,83
< int idx = destRegIdx(i);
< if (idx < Misc_Reg_Base) {
---
> RegId reg = destRegIdx(i);
> if (reg.regClass != MiscRegClass) {
87,88c86
< idx -= Misc_Reg_Base;
< if (idx == MISCREG_CPSR) {
---
> if (reg.regIdx == MISCREG_CPSR) {
93c91
< if (idx == MISCREG_SPSR) {
---
> if (reg.regIdx == MISCREG_SPSR) {
145c143
< printReg(ss, op1);
---
> printIntReg(ss, op1);
154c152
< printReg(ss, dest);
---
> printIntReg(ss, dest);
156c154
< printReg(ss, dest2);
---
> printIntReg(ss, dest2);
158c156
< printReg(ss, op1);
---
> printIntReg(ss, op1);
167c165
< printReg(ss, dest);
---
> printIntReg(ss, dest);
169c167
< printReg(ss, op1);
---
> printIntReg(ss, op1);
171c169
< printReg(ss, op2);
---
> printIntReg(ss, op2);
189c187
< printReg(ss, dest);
---
> printIntReg(ss, dest);
199c197
< printReg(ss, dest);
---
> printIntReg(ss, dest);
201c199
< printReg(ss, op1);
---
> printIntReg(ss, op1);
210c208
< printReg(ss, dest);
---
> printIntReg(ss, dest);
212c210
< printReg(ss, op1);
---
> printIntReg(ss, op1);
214c212
< printReg(ss, op2);
---
> printIntReg(ss, op2);
224c222
< printReg(ss, dest);
---
> printIntReg(ss, dest);
226c224
< printReg(ss, op1);
---
> printIntReg(ss, op1);
228c226
< printReg(ss, op2);
---
> printIntReg(ss, op2);
230c228
< printReg(ss, op3);
---
> printIntReg(ss, op3);
239c237
< printReg(ss, dest);
---
> printIntReg(ss, dest);
241c239
< printReg(ss, op1);
---
> printIntReg(ss, op1);
243c241
< printReg(ss, op2);
---
> printIntReg(ss, op2);
252c250
< printReg(ss, dest);
---
> printIntReg(ss, dest);
254c252
< printReg(ss, op1);
---
> printIntReg(ss, op1);
264c262
< printReg(ss, dest);
---
> printIntReg(ss, dest);
266c264
< printReg(ss, op1);
---
> printIntReg(ss, op1);
276c274
< printReg(ss, dest);
---
> printIntReg(ss, dest);
278c276
< printReg(ss, op1);
---
> printIntReg(ss, op1);
288c286
< printReg(ss, dest);
---
> printIntReg(ss, dest);
298c296
< printReg(ss, dest);
---
> printIntReg(ss, dest);
300c298
< printReg(ss, op1);
---
> printIntReg(ss, op1);
310c308
< printReg(ss, dest);
---
> printIntReg(ss, dest);
312c310
< printReg(ss, op1);
---
> printIntReg(ss, op1);
321c319
< printReg(ss, dest);
---
> printIntReg(ss, dest);
324c322
< printReg(ss, op1);
---
> printIntReg(ss, op1);