1/* 2 * Copyright (c) 2010, 2012-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are 17 * met: redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer; 19 * redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution; 22 * neither the name of the copyright holders nor the names of its 23 * contributors may be used to endorse or promote products derived from 24 * this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Gabe Black 39 */ 40 41#include "arch/arm/insts/misc.hh" 42 43#include "cpu/reg_class.hh" 44 45std::string 46MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 47{ 48 std::stringstream ss; 49 printMnemonic(ss);
| 1/* 2 * Copyright (c) 2010, 2012-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are 17 * met: redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer; 19 * redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution; 22 * neither the name of the copyright holders nor the names of its 23 * contributors may be used to endorse or promote products derived from 24 * this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Gabe Black 39 */ 40 41#include "arch/arm/insts/misc.hh" 42 43#include "cpu/reg_class.hh" 44 45std::string 46MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 47{ 48 std::stringstream ss; 49 printMnemonic(ss);
|
50 printReg(ss, dest);
| 50 printIntReg(ss, dest);
|
51 ss << ", "; 52 bool foundPsr = false; 53 for (unsigned i = 0; i < numSrcRegs(); i++) {
| 51 ss << ", "; 52 bool foundPsr = false; 53 for (unsigned i = 0; i < numSrcRegs(); i++) {
|
54 RegIndex idx = srcRegIdx(i); 55 RegIndex rel_idx; 56 if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
| 54 RegId reg = srcRegIdx(i); 55 if (reg.regClass != MiscRegClass) {
|
57 continue; 58 }
| 56 continue; 57 }
|
59 if (rel_idx == MISCREG_CPSR) {
| 58 if (reg.regIdx == MISCREG_CPSR) {
|
60 ss << "cpsr"; 61 foundPsr = true; 62 break; 63 }
| 59 ss << "cpsr"; 60 foundPsr = true; 61 break; 62 }
|
64 if (rel_idx == MISCREG_SPSR) {
| 63 if (reg.regIdx == MISCREG_SPSR) {
|
65 ss << "spsr"; 66 foundPsr = true; 67 break; 68 } 69 } 70 if (!foundPsr) { 71 ss << "????"; 72 } 73 return ss.str(); 74} 75 76void 77MsrBase::printMsrBase(std::ostream &os) const 78{ 79 printMnemonic(os); 80 bool apsr = false; 81 bool foundPsr = false; 82 for (unsigned i = 0; i < numDestRegs(); i++) {
| 64 ss << "spsr"; 65 foundPsr = true; 66 break; 67 } 68 } 69 if (!foundPsr) { 70 ss << "????"; 71 } 72 return ss.str(); 73} 74 75void 76MsrBase::printMsrBase(std::ostream &os) const 77{ 78 printMnemonic(os); 79 bool apsr = false; 80 bool foundPsr = false; 81 for (unsigned i = 0; i < numDestRegs(); i++) {
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83 int idx = destRegIdx(i); 84 if (idx < Misc_Reg_Base) {
| 82 RegId reg = destRegIdx(i); 83 if (reg.regClass != MiscRegClass) {
|
85 continue; 86 }
| 84 continue; 85 }
|
87 idx -= Misc_Reg_Base; 88 if (idx == MISCREG_CPSR) {
| 86 if (reg.regIdx == MISCREG_CPSR) {
|
89 os << "cpsr_"; 90 foundPsr = true; 91 break; 92 }
| 87 os << "cpsr_"; 88 foundPsr = true; 89 break; 90 }
|
93 if (idx == MISCREG_SPSR) {
| 91 if (reg.regIdx == MISCREG_SPSR) {
|
94 if (bits(byteMask, 1, 0)) { 95 os << "spsr_"; 96 } else { 97 os << "apsr_"; 98 apsr = true; 99 } 100 foundPsr = true; 101 break; 102 } 103 } 104 if (!foundPsr) { 105 os << "????"; 106 return; 107 } 108 if (bits(byteMask, 3)) { 109 if (apsr) { 110 os << "nzcvq"; 111 } else { 112 os << "f"; 113 } 114 } 115 if (bits(byteMask, 2)) { 116 if (apsr) { 117 os << "g"; 118 } else { 119 os << "s"; 120 } 121 } 122 if (bits(byteMask, 1)) { 123 os << "x"; 124 } 125 if (bits(byteMask, 0)) { 126 os << "c"; 127 } 128} 129 130std::string 131MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 132{ 133 std::stringstream ss; 134 printMsrBase(ss); 135 ccprintf(ss, ", #%#x", imm); 136 return ss.str(); 137} 138 139std::string 140MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 141{ 142 std::stringstream ss; 143 printMsrBase(ss); 144 ss << ", ";
| 92 if (bits(byteMask, 1, 0)) { 93 os << "spsr_"; 94 } else { 95 os << "apsr_"; 96 apsr = true; 97 } 98 foundPsr = true; 99 break; 100 } 101 } 102 if (!foundPsr) { 103 os << "????"; 104 return; 105 } 106 if (bits(byteMask, 3)) { 107 if (apsr) { 108 os << "nzcvq"; 109 } else { 110 os << "f"; 111 } 112 } 113 if (bits(byteMask, 2)) { 114 if (apsr) { 115 os << "g"; 116 } else { 117 os << "s"; 118 } 119 } 120 if (bits(byteMask, 1)) { 121 os << "x"; 122 } 123 if (bits(byteMask, 0)) { 124 os << "c"; 125 } 126} 127 128std::string 129MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 130{ 131 std::stringstream ss; 132 printMsrBase(ss); 133 ccprintf(ss, ", #%#x", imm); 134 return ss.str(); 135} 136 137std::string 138MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 139{ 140 std::stringstream ss; 141 printMsrBase(ss); 142 ss << ", ";
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145 printReg(ss, op1);
| 143 printIntReg(ss, op1);
|
146 return ss.str(); 147} 148 149std::string 150MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 151{ 152 std::stringstream ss; 153 printMnemonic(ss);
| 144 return ss.str(); 145} 146 147std::string 148MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 149{ 150 std::stringstream ss; 151 printMnemonic(ss);
|
154 printReg(ss, dest);
| 152 printIntReg(ss, dest);
|
155 ss << ", ";
| 153 ss << ", ";
|
156 printReg(ss, dest2);
| 154 printIntReg(ss, dest2);
|
157 ss << ", ";
| 155 ss << ", ";
|
158 printReg(ss, op1);
| 156 printIntReg(ss, op1);
|
159 return ss.str(); 160} 161 162std::string 163McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 164{ 165 std::stringstream ss; 166 printMnemonic(ss);
| 157 return ss.str(); 158} 159 160std::string 161McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 162{ 163 std::stringstream ss; 164 printMnemonic(ss);
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167 printReg(ss, dest);
| 165 printIntReg(ss, dest);
|
168 ss << ", ";
| 166 ss << ", ";
|
169 printReg(ss, op1);
| 167 printIntReg(ss, op1);
|
170 ss << ", ";
| 168 ss << ", ";
|
171 printReg(ss, op2);
| 169 printIntReg(ss, op2);
|
172 return ss.str(); 173} 174 175std::string 176ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 177{ 178 std::stringstream ss; 179 printMnemonic(ss); 180 ccprintf(ss, "#%d", imm); 181 return ss.str(); 182} 183 184std::string 185RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 186{ 187 std::stringstream ss; 188 printMnemonic(ss);
| 170 return ss.str(); 171} 172 173std::string 174ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 175{ 176 std::stringstream ss; 177 printMnemonic(ss); 178 ccprintf(ss, "#%d", imm); 179 return ss.str(); 180} 181 182std::string 183RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 184{ 185 std::stringstream ss; 186 printMnemonic(ss);
|
189 printReg(ss, dest);
| 187 printIntReg(ss, dest);
|
190 ccprintf(ss, ", #%d", imm); 191 return ss.str(); 192} 193 194std::string 195RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 196{ 197 std::stringstream ss; 198 printMnemonic(ss);
| 188 ccprintf(ss, ", #%d", imm); 189 return ss.str(); 190} 191 192std::string 193RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 194{ 195 std::stringstream ss; 196 printMnemonic(ss);
|
199 printReg(ss, dest);
| 197 printIntReg(ss, dest);
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200 ss << ", ";
| 198 ss << ", ";
|
201 printReg(ss, op1);
| 199 printIntReg(ss, op1);
|
202 return ss.str(); 203} 204 205std::string 206RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 207{ 208 std::stringstream ss; 209 printMnemonic(ss);
| 200 return ss.str(); 201} 202 203std::string 204RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 205{ 206 std::stringstream ss; 207 printMnemonic(ss);
|
210 printReg(ss, dest);
| 208 printIntReg(ss, dest);
|
211 ss << ", ";
| 209 ss << ", ";
|
212 printReg(ss, op1);
| 210 printIntReg(ss, op1);
|
213 ss << ", ";
| 211 ss << ", ";
|
214 printReg(ss, op2);
| 212 printIntReg(ss, op2);
|
215 ccprintf(ss, ", #%d", imm); 216 return ss.str(); 217} 218 219std::string 220RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 221{ 222 std::stringstream ss; 223 printMnemonic(ss);
| 213 ccprintf(ss, ", #%d", imm); 214 return ss.str(); 215} 216 217std::string 218RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 219{ 220 std::stringstream ss; 221 printMnemonic(ss);
|
224 printReg(ss, dest);
| 222 printIntReg(ss, dest);
|
225 ss << ", ";
| 223 ss << ", ";
|
226 printReg(ss, op1);
| 224 printIntReg(ss, op1);
|
227 ss << ", ";
| 225 ss << ", ";
|
228 printReg(ss, op2);
| 226 printIntReg(ss, op2);
|
229 ss << ", ";
| 227 ss << ", ";
|
230 printReg(ss, op3);
| 228 printIntReg(ss, op3);
|
231 return ss.str(); 232} 233 234std::string 235RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 236{ 237 std::stringstream ss; 238 printMnemonic(ss);
| 229 return ss.str(); 230} 231 232std::string 233RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 234{ 235 std::stringstream ss; 236 printMnemonic(ss);
|
239 printReg(ss, dest);
| 237 printIntReg(ss, dest);
|
240 ss << ", ";
| 238 ss << ", ";
|
241 printReg(ss, op1);
| 239 printIntReg(ss, op1);
|
242 ss << ", ";
| 240 ss << ", ";
|
243 printReg(ss, op2);
| 241 printIntReg(ss, op2);
|
244 return ss.str(); 245} 246 247std::string 248RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 249{ 250 std::stringstream ss; 251 printMnemonic(ss);
| 242 return ss.str(); 243} 244 245std::string 246RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 247{ 248 std::stringstream ss; 249 printMnemonic(ss);
|
252 printReg(ss, dest);
| 250 printIntReg(ss, dest);
|
253 ss << ", ";
| 251 ss << ", ";
|
254 printReg(ss, op1);
| 252 printIntReg(ss, op1);
|
255 ccprintf(ss, ", #%d", imm); 256 return ss.str(); 257} 258 259std::string 260MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 261{ 262 std::stringstream ss; 263 printMnemonic(ss);
| 253 ccprintf(ss, ", #%d", imm); 254 return ss.str(); 255} 256 257std::string 258MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 259{ 260 std::stringstream ss; 261 printMnemonic(ss);
|
264 printReg(ss, dest);
| 262 printIntReg(ss, dest);
|
265 ss << ", ";
| 263 ss << ", ";
|
266 printReg(ss, op1);
| 264 printIntReg(ss, op1);
|
267 ccprintf(ss, ", #%d", imm); 268 return ss.str(); 269} 270 271std::string 272RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 273{ 274 std::stringstream ss; 275 printMnemonic(ss);
| 265 ccprintf(ss, ", #%d", imm); 266 return ss.str(); 267} 268 269std::string 270RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 271{ 272 std::stringstream ss; 273 printMnemonic(ss);
|
276 printReg(ss, dest);
| 274 printIntReg(ss, dest);
|
277 ss << ", ";
| 275 ss << ", ";
|
278 printReg(ss, op1);
| 276 printIntReg(ss, op1);
|
279 ccprintf(ss, ", #%d", imm); 280 return ss.str(); 281} 282 283std::string 284RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 285{ 286 std::stringstream ss; 287 printMnemonic(ss);
| 277 ccprintf(ss, ", #%d", imm); 278 return ss.str(); 279} 280 281std::string 282RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 283{ 284 std::stringstream ss; 285 printMnemonic(ss);
|
288 printReg(ss, dest);
| 286 printIntReg(ss, dest);
|
289 ccprintf(ss, ", #%d, #%d", imm1, imm2); 290 return ss.str(); 291} 292 293std::string 294RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 295{ 296 std::stringstream ss; 297 printMnemonic(ss);
| 287 ccprintf(ss, ", #%d, #%d", imm1, imm2); 288 return ss.str(); 289} 290 291std::string 292RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 293{ 294 std::stringstream ss; 295 printMnemonic(ss);
|
298 printReg(ss, dest);
| 296 printIntReg(ss, dest);
|
299 ss << ", ";
| 297 ss << ", ";
|
300 printReg(ss, op1);
| 298 printIntReg(ss, op1);
|
301 ccprintf(ss, ", #%d, #%d", imm1, imm2); 302 return ss.str(); 303} 304 305std::string 306RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 307{ 308 std::stringstream ss; 309 printMnemonic(ss);
| 299 ccprintf(ss, ", #%d, #%d", imm1, imm2); 300 return ss.str(); 301} 302 303std::string 304RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 305{ 306 std::stringstream ss; 307 printMnemonic(ss);
|
310 printReg(ss, dest);
| 308 printIntReg(ss, dest);
|
311 ccprintf(ss, ", #%d, ", imm);
| 309 ccprintf(ss, ", #%d, ", imm);
|
312 printReg(ss, op1);
| 310 printIntReg(ss, op1);
|
313 return ss.str(); 314} 315 316std::string 317RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 318{ 319 std::stringstream ss; 320 printMnemonic(ss);
| 311 return ss.str(); 312} 313 314std::string 315RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 316{ 317 std::stringstream ss; 318 printMnemonic(ss);
|
321 printReg(ss, dest);
| 319 printIntReg(ss, dest);
|
322 ccprintf(ss, ", #%d, ", imm); 323 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
| 320 ccprintf(ss, ", #%d, ", imm); 321 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
|
324 printReg(ss, op1);
| 322 printIntReg(ss, op1);
|
325 return ss.str(); 326} 327 328std::string 329UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 330{ 331 return csprintf("%-10s (inst %#08x)", "unknown", machInst); 332}
| 323 return ss.str(); 324} 325 326std::string 327UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 328{ 329 return csprintf("%-10s (inst %#08x)", "unknown", machInst); 330}
|