1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#include "arch/arm/insts/misc.hh"
42#include "cpu/reg_class.hh"
43
44std::string
45MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
46{
47 std::stringstream ss;
48 printMnemonic(ss);
49 printReg(ss, dest);
50 ss << ", ";
51 bool foundPsr = false;
52 for (unsigned i = 0; i < numSrcRegs(); i++) {
53 RegIndex idx = srcRegIdx(i);
54 RegIndex rel_idx;
55 if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
56 continue;
57 }
58 if (rel_idx == MISCREG_CPSR) {
59 ss << "cpsr";
60 foundPsr = true;
61 break;
62 }
63 if (rel_idx == MISCREG_SPSR) {
64 ss << "spsr";
65 foundPsr = true;
66 break;
67 }
68 }
69 if (!foundPsr) {
70 ss << "????";
71 }
72 return ss.str();
73}
74
75void
76MsrBase::printMsrBase(std::ostream &os) const
77{
78 printMnemonic(os);
79 bool apsr = false;
80 bool foundPsr = false;
81 for (unsigned i = 0; i < numDestRegs(); i++) {
82 int idx = destRegIdx(i);
83 if (idx < Misc_Reg_Base) {
84 continue;
85 }
86 idx -= Misc_Reg_Base;
87 if (idx == MISCREG_CPSR) {
88 os << "cpsr_";
89 foundPsr = true;
90 break;
91 }
92 if (idx == MISCREG_SPSR) {
93 if (bits(byteMask, 1, 0)) {
94 os << "spsr_";
95 } else {
96 os << "apsr_";
97 apsr = true;
98 }
99 foundPsr = true;
100 break;
101 }
102 }
103 if (!foundPsr) {
104 os << "????";
105 return;
106 }
107 if (bits(byteMask, 3)) {
108 if (apsr) {
109 os << "nzcvq";
110 } else {
111 os << "f";
112 }
113 }
114 if (bits(byteMask, 2)) {
115 if (apsr) {
116 os << "g";
117 } else {
118 os << "s";
119 }
120 }
121 if (bits(byteMask, 1)) {
122 os << "x";
123 }
124 if (bits(byteMask, 0)) {
125 os << "c";
126 }
127}
128
129std::string
130MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
131{
132 std::stringstream ss;
133 printMsrBase(ss);
134 ccprintf(ss, ", #%#x", imm);
135 return ss.str();
136}
137
138std::string
139MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
140{
141 std::stringstream ss;
142 printMsrBase(ss);
143 ss << ", ";
144 printReg(ss, op1);
145 return ss.str();
146}
147
148std::string
149MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
150{
151 std::stringstream ss;
152 printMnemonic(ss);
153 printReg(ss, dest);
154 ss << ", ";
155 printReg(ss, dest2);
156 ss << ", ";
157 printReg(ss, op1);
158 return ss.str();
159}
160
161std::string
162McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
163{
164 std::stringstream ss;
165 printMnemonic(ss);
166 printReg(ss, dest);
167 ss << ", ";
168 printReg(ss, op1);
169 ss << ", ";
170 printReg(ss, op2);
171 return ss.str();
172}
173
174std::string
175ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
176{
177 std::stringstream ss;
178 printMnemonic(ss);
179 ccprintf(ss, "#%d", imm);
180 return ss.str();
181}
182
183std::string
184RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
185{
186 std::stringstream ss;
187 printMnemonic(ss);
188 printReg(ss, dest);
189 ccprintf(ss, ", #%d", imm);
190 return ss.str();
191}
192
193std::string
194RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
195{
196 std::stringstream ss;
197 printMnemonic(ss);
198 printReg(ss, dest);
199 ss << ", ";
200 printReg(ss, op1);
201 return ss.str();
202}
203
204std::string
205RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
206{
207 std::stringstream ss;
208 printMnemonic(ss);
209 printReg(ss, dest);
210 ss << ", ";
211 printReg(ss, op1);
212 ss << ", ";
213 printReg(ss, op2);
214 ccprintf(ss, ", #%d", imm);
215 return ss.str();
216}
217
218std::string
219RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
220{
221 std::stringstream ss;
222 printMnemonic(ss);
223 printReg(ss, dest);
224 ss << ", ";
225 printReg(ss, op1);
226 ss << ", ";
227 printReg(ss, op2);
228 ss << ", ";
229 printReg(ss, op3);
230 return ss.str();
231}
232
233std::string
234RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
235{
236 std::stringstream ss;
237 printMnemonic(ss);
238 printReg(ss, dest);
239 ss << ", ";
240 printReg(ss, op1);
241 ss << ", ";
242 printReg(ss, op2);
243 return ss.str();
244}
245
246std::string
247RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
248{
249 std::stringstream ss;
250 printMnemonic(ss);
251 printReg(ss, dest);
252 ss << ", ";
253 printReg(ss, op1);
254 ccprintf(ss, ", #%d", imm);
255 return ss.str();
256}
257
258std::string
259MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
260{
261 std::stringstream ss;
262 printMnemonic(ss);
263 printReg(ss, dest);
264 ss << ", ";
265 printReg(ss, op1);
266 ccprintf(ss, ", #%d", imm);
267 return ss.str();
268}
269
270std::string
271RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
272{
273 std::stringstream ss;
274 printMnemonic(ss);
275 printReg(ss, dest);
276 ss << ", ";
277 printReg(ss, op1);
278 ccprintf(ss, ", #%d", imm);
279 return ss.str();
280}
281
282std::string
283RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
284{
285 std::stringstream ss;
286 printMnemonic(ss);
287 printReg(ss, dest);
288 ccprintf(ss, ", #%d, #%d", imm1, imm2);
289 return ss.str();
290}
291
292std::string
293RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
294{
295 std::stringstream ss;
296 printMnemonic(ss);
297 printReg(ss, dest);
298 ss << ", ";
299 printReg(ss, op1);
300 ccprintf(ss, ", #%d, #%d", imm1, imm2);
301 return ss.str();
302}
303
304std::string
305RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
306{
307 std::stringstream ss;
308 printMnemonic(ss);
309 printReg(ss, dest);
310 ccprintf(ss, ", #%d, ", imm);
311 printReg(ss, op1);
312 return ss.str();
313}
314
315std::string
316RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
317{
318 std::stringstream ss;
319 printMnemonic(ss);
320 printReg(ss, dest);
321 ccprintf(ss, ", #%d, ", imm);
322 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
323 printReg(ss, op1);
324 return ss.str();
325}
326
327std::string
328UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
329{
330 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
331}