1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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254 return ss.str();
255}
256
257std::string
258MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
259{
260 std::stringstream ss;
261 printMnemonic(ss);
262 printIntReg(ss, dest);
263 ss << ", ";
264 printIntReg(ss, op1);
265 ccprintf(ss, ", #%d", imm);
266 return ss.str();
267}
268
269std::string
270RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
271{
272 std::stringstream ss;
273 printMnemonic(ss);
274 printIntReg(ss, dest);
275 ss << ", ";
276 printIntReg(ss, op1);
277 ccprintf(ss, ", #%d", imm);
278 return ss.str();
279}
280
281std::string
282RegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
283{
284 std::stringstream ss;
285 printMnemonic(ss);

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